• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.9
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• pp.78-85
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• 2000

A new analytical VLSI interconnect delay model is presented and its accuracy is experimentally verified. In the model, the transmission line parameter variations due to skin effect, proximity effect, and silicon substrate effect are taken into account. That is, the circuit model of the interconnect line that includes these effects is newly developed and analyzed. For the model verification, test patterns combined the coplanar structure with microstrip were designed by using 0.35${\mu}m$ CMOS process technology. It is shown that the accuracy of the model is less than about 10% error.

• 한국해양학회지
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• v.21 no.1
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• pp.1-12
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• 1986

A total of 40 surface samples(12 from the intertidal flat and 28 from the subtidal zone) from Gwangyang Bay, southern coast of the Korean Peninsula show a strong negative relationship between the total foraminiferal abundance and the ratios of the live to the total(L/T) assemblages. This suggests that the foraminiferal abundance is dependent on the dilution due to the input of detrital sediments, and that the L/T ratios show the relative rate of sedimentation in the study area. The intertidal flat and delta area are characterized by the relatively high sedimentation compared to the inner bay and shallow subtidal zone, and three major tidal channels where relatively low and no sedimentation is noted, respectively. Bathymetric occurrence of the species shows distinct boundaries at 9m, and between 21 and 30m, respectively. Cluster analysis shows three biotopes;intertidal flat including delay, inner bay and shallow subtidal zone, and major tidal channels. This suggests that these biotopes are formed by the ecology of the foraminifers as well as by the sedimentological setting of the study area. Several problems in relation to the relative rate of sedimentation inferred from the L/T ratios are briefly discussed.

• Journal of The Korean Society of Inherited Metabolic disease
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• v.11 no.1
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• pp.88-98
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• 2011

Lesch-Nyhan syndrome is a X-linked recessive disorder caused by a deficiency of the enzyme hypoxanthine-guanidine phosphoribosyltransferase (HPRT), enzyme to recycle purines. Case history: born induced vaginal delivery at 40 weeks complicated by premature membrane ruputure, body weight 2.820 gm. He showed failure to thrive showing severe protein aversion like milk products and pink daper. Developmental delay revealing rolling over at 10.5 month, followed by regression. Seizure at 2 months, His poor oral feeding was lifelong problem. Weak crying, spastic, choreoathetoid movement. Self mutilating behavior noted and diagnosed at age 3 years. No family history of consanguinity and neurological disorders. Method: Laboratory test, physical exam, imaging study and molecular. Clinical follow up Treat ment with allopurinol. Result: uric acid 10.5 mg/dL (N 3.5-7.9), APRT 151.1uM/ min/ml pro(25.7-101), HPRT 7.6 (N 233.5-701) and c.151C>T hemizygote (p,Arg51X). Abdominal sonogram showed staghorn calculi in both kidneys, brain MRI brain atrophy. Clinical follow up showed, seizure at 2 mo, developmental delay (head control and, rolling over at at 11mo, pointing body part at 2 yr 7 mo, eye hand coordination at 2 y 11mo,creeping at 3 y 7 mo, speaking words at 6 y 6 mo ),and developmental regression at 3 yr of age. Sleeping problem including insomnia and severe constipation. Self mutilating behavior (lip bite) started at 2.5 yr, neurologic sx including intermittent upward gaze accompanied by swallowing difficulty at 3 y 7 mo grand mal seizure at 4.5 yr and spastic extremity and trunchal hypotonia and choleoathetoid movement and ataxia at 6.5 yr. Scoliosis with severe spasticity at 9 yr 9 mo. Acute life threatening episode with irregular breathing at 9 yr and 9 mo, Emaciation and nephrolithiasis and recurrent pneumonia. Died suddenly at 10 yr 3 mo. Conclusion: life long feeding problem, chronic gut motility dysfunction, sleeping difficulty and progressing neurologic deterioration and nephrolithiasis despite normal serum uric acid maintence by allopurinol treatment.

• Journal of the Korean Society of Food Science and Nutrition
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• v.43 no.1
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• pp.24-29
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• 2014

The effects of Lycii fructus and Lycii folium on osteoporosis and serum cholesterol levels were tested in ovariectomized (OVX) rats. Twenty-four female Sprague-Dawley rats were divided into four groups: Sham group (sham-operated), Control group (OVX, ovariectomized model), LCF group (Ovx+Lycii fructus extract), and LCL group (OVX+Lycium folium extract). After 8 weeks, the OVX ($330{\pm}5.39$ g), LCF ($315{\pm}2.99$ g), and LCL ($318{\pm}2.06$ g) groups showed increased body weight compared with sham group ($281{\pm}1.71$ g). The levels of serum osteocalcin (OC) also increased in the LCF ($444.6{\pm}26.9$ ng/mL) and LCL ($407{\pm}18.9$ ng/mL) groups compared with the OVX group ($107{\pm}3.52$ ng/mL). The activities of serum alkaline phosphatase (ALP) increased in the LCF ($108{\pm}2.7$ U/L) and LCL ($407{\pm}18.9$ ng/mL) groups compared with the OVX group ($95{\pm}2.9$ U/L). Stereomicroscopy found that the low bone density that developed in the OVX group was significantly reversed in the LCF and LCL groups after 8 weeks. We also obtained molecular-based in vivo evidence that supports a mechanism of action involving novel estrogen receptor ($ER{\alpha}$) modulator in the uterus. We found that expression of ER${\alpha}$ mRNA in the OVX rat uterus was elevated by Lycium chinense. These results suggest that Lycii fructus and Lycii folium administered to rats during 8 weeks after oophorectomy may partially recover postmenopausal osteoporosis or delay the progression of osteoporotic changes.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.37-44
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• 2008

This paper presents a 5.8 GHz PLL using high-speed ring oscillator for WLAN. The proposed ring oscillator has been designed using the negative skewed delay scheme and for differential mode operation. Therefore, the oscillator is insensitive to power-supply-injected noise, and it has the merit of low 1/f noise because tail current sources are not used. The output frequency ranges from 5.13 to 7.04 GHz with the control voltage varing from 0 to 1.8 V. The proposed PLL circuits have been designed, simulated, and proved using 0.18 um 1.8 V TSMC CMOS library. At the operation frequency of 5.8 GHz, the locking time is 2.5 us and the simulated power consumption is 59.9 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.5
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• pp.397-400
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• 2018

This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.

• Journal of IKEEE
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• v.24 no.4
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• pp.1074-1080
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• 2020

This paper proposes a digitally controlled buck converter insensitive to process, voltage and temperature and capable of three modes of operation depending on the state of the output voltage. Conventional digital-controlled buck converters utilized A/D converters, counters and delay line circuits for accurate output voltage control, resulting in increasing the number of counter and delay line bits. This problem can be resolved by employing the 8-bit and 16-bit bidirectional shift registers, and this design technique leads a buck converter to be able to control duty ratio up to 128-bit resolution. The proposed buck converter was designed and fabricated with a CMOS 180 nano-meter 1-poly 6-metal process, generating an output voltage of 0.9 to 1.8V with the input voltage range of 2.7V to 3.6V, a ripple voltage of 30mV, and a power efficiency of up to 92.3%. The transient response speed of the proposed circuit was measured to be 4us.

• KIEAE Journal
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• v.16 no.1
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• pp.67-71
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• 2016

Purpose: There is a growing interest in rainwater runoff reduction effect of green roof, as flooding caused by increasing impervious surface is becoming more and more frequent in urban areas. This study was conducted to prove runoff reduction and runoff delay effect of the retentive green roof and to investigate its influencing factors to the rainfall events that occurred in the summer of 2013. Method: The experiment intended to monitor the runoff quantity of the retentive green roof($140m^2$) and normal roof($100m^2$) in #35 building in Seoul National University, Seoul, Korea for 75 days in 2013. Result: On analysis of 9 rainfall events, it showed that the retentive green roof has 24.8~100% of runoff reduction ratio, 21.2~100% of peak flow reduction ratio, 0.5~3.75 hours of peak delay, and $1.8{\sim}7.2m^3$ of retaining capacity in an area of $140m^2$. It shows different results depending on rainfall and antecedent dry days. The results show that runoff reduction effect is effective when the rainfall is less than 50 mm and antecedent dry day is longer than five days on average. By installing retentive green roofs on buildings, it can help mitigate urban floods and rehabilitate urban water cycle.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1538-1544
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• 2006

This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.1-9
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• 2009

A full adders is an important component in applications of digital signal processors and microprocessors. Thus it is imperative to improve the power dissipation and operating speed for designing a full adder. We propose a new adder with modified version of conventional static CMOS and pass transistor logic. The carry-out generation circuit of the proposed full adder is different from the conventional XOR-XNOR structure. The output Cout of module III is generated from input A, B and Cin directly without passing through module I as in conventional structure. Thus output Cout is faster by reducing operation step. The proposed module III uses the static CMOS logic style, which results full-swing operation and good driving capability. The proposed 1bit full adder has the advantages over the conventional static CMOS, CPL, TGA, TFA, HPSC, 14T, and TSAC logic. The delay time is improved by 4.3% comparing to the best value known. PDP(power delay product) is improved by 9.8% comparing to the best value. Simulation has been carried out using a $0.18{\mu}m$ CMOS design rule for simulation purposes. The physical design has been verified using HSPICE.