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http://dx.doi.org/10.5515/KJKIEES.2018.29.5.397

30~46 GHz Wideband Amplifier Using 65 nm CMOS  

Shin, Miae (Department of Electronic and Computer Engineering, Sungkyunkwan University)
Seo, Munkyo (Department of Electronic and Computer Engineering, Sungkyunkwan University)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.29, no.5, 2018 , pp. 397-400 More about this Journal
Abstract
This paper presents a miniaturized 65 nm CMOS 30~46 GHz wideband amplifier. To minimize the chip area, coupled inductors are used in the matching networks. The measurement shows that the fabricated amplifier exhibits 9.3 dB of peak gain, 16 GHz of 3 dB bandwidth, and 42 % fractional bandwidth. The measured input and output return losses were more than 10 dB at 35.8~46.0 GHz and 28.6~37.8 GHz, respectively. The chip consumes 42 mW at 1.2 V. The measured group delay variation is 19.1 ps within the 3 dB bandwidth and the chip size excluding the pads is $0.09mm^2$.
Keywords
Wideband Amplifier; Fractional Bandwidth; Coupled Inductor; Group Delay; Q-Band;
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