• Journal of IKEEE
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• v.23 no.2
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• pp.681-686
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• 2019

This paper proposes a CMOS temperature sensor using inverter delay chains of the same size based on the pulse shrinking method. A temperature-pulse converter (TPC) uses two different temperature delay lines with inverter chains to generate a pulse in proportion to temperature, and a time-digital converter (TDC) shrinks the pulse using inverter chains of the same size to convert pulse width into a digital value to be insensitive to process changes. The chip was implemented with a $0.49{\mu}m{\times}0.23{\mu}m$ area using a $0.35{\mu}m$ CMOS process with a supply voltage of 3.3V. The measurement results show a resolution of $0.24^{\circ}C/bit$ for 9-bit data for a temperature sensor range of $0^{\circ}C$ to $100^{\circ}C$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.1-8
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• 1998

In this paper, we designed a low power 8bit ELM adder with static CMOS and hybrid logic styles on a chip. The designed 8bit ELM adder with both logic styles was fabricated in a 0.8$\mu\textrm{m}$ single-poly double-metal, LG CMOS process and tested. Hybrid logic style consists of CCPL(Combinative Complementary Pass-transistor Logic), Wang's XOR gate and static CMOS for critical path which determines the speed of ELM adder. As a result of chip test, the ELM adder with hybrid logic style is superior to the one with static CMOS by 9.29% in power consumption, 14.9% in delay time and 22.8% in PDP(Power Delay Product) at 5.0V supply voltage, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.9
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• pp.9-16
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• 2004

This paper proposes a performance analysis model of security servers comprising IPSec accelerators. The proposed model is based on a M/M1 queueing system with traffic load of Poisson distribution. The decoding delay has been defined to cover parameters characterizing hardware of security sorrels. Decoding delay values of a commercial IPSec accelerator are extracted yielding less than 15% differences from measured data. The extracted data are used to simulate the server system with the proposed model. The simulated performance of the cryptographic processor BCM5820 is around 75% of the published claimed level. The performance degradation of 3.125% and 14.28% are observed for 64byte packets and 1024byte packets, respectively.

• Journal of Institute of Control, Robotics and Systems
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• v.21 no.4
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• pp.385-390
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• 2015

Quay cranes are considered core equipment for container terminal operation. However, unmanned operation systems have not as yet been announced due to the technological difficulties of implementation. In this paper, we developed a wireless controller to control a quay crane simulator remotely and conducted its performance test, a first step toward unmanned operation of quay cranes. The communication delay of a developed wireless controller was about 9.4ms on average while that of existing wired controllers was about 5.6ms. The same functions were implemented and tested on a smart phone where the average communication delay was 7.3ms. In addition, to apply the developed system into a real environment, we proposed a network architecture based on IEEE 802.11ac and carried out its performance evaluation. When the distance between two nodes was 50m apart, the throughputs of the TCP (Transmission Control Protocol) and UDP (User Datagram Protocol) were 57Mbps and 189Mbps, respectively. The communication delay of the control data was 9.1ms through the TCP channel. These results reveal the proper working of remote quay crane operation if we adopt the IEEE 802.11ac network.

• Explosives and Blasting
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• v.32 no.3
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• pp.1-9
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• 2014

Since the rock fragmentation from a bench blasting can affect the subsequent processes including loading, hauling and crushing, its control is essential for the assessment of blasting efficiency as well as production cost. In this study, the delay time could be precisely controlled by using electronic detonators. The rock fragmentations resulted from the blastings with different delay times of 1, 2, 3, 4, 5, 7 and 10ms per each meter of burden were measured from full scale field tests in a limestone mine. The results showed that the optimum delay time for minimum fragmentation was approximately 6ms/m. From the analysis of fragmentation size distribution, it was possible to find that delay time can be a parameter on rock fragmentation and thus it would be possible to control rock fragmentation by adjusting delay time.

• Clinical and Experimental Pediatrics
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• v.60 no.9
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• pp.282-289
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• 2017

Purpose: Recent advancements in molecular techniques have greatly contributed to the discovery of genetic causes of unexplained developmental delay. Here, we describe the results of array comparative genomic hybridization (CGH) and the clinical features of 27 patients with global developmental delay. Methods: We included 27 children who fulfilled the following criteria: Korean children under 6 years with global developmental delay; children who had at least one or more physical or neurological problem other than global developmental delay; and patients in whom both array CGH and G-banded karyotyping tests were performed. Results: Fifteen male and 12 female patients with a mean age of $29.3{\pm}17.6months$ were included. The most common physical and neurological abnormalities were facial dysmorphism (n=16), epilepsy (n=7), and hypotonia (n=7). Pathogenic copy number variation results were observed in 4 patients (14.8%): 18.73 Mb dup(2)(p24.2p25.3) and 1.62 Mb del(20p13) (patient 1); 22.31 Mb dup(2) (p22.3p25.1) and 4.01 Mb dup(2)(p21p22.1) (patient 2); 12.08 Mb del(4)(q22.1q24) (patient 3); and 1.19 Mb del(1)(q21.1) (patient 4). One patient (3.7%) displayed a variant of uncertain significance. Four patients (14.8%) displayed discordance between G-banded karyotyping and array CGH results. Among patients with normal array CGH results, 4 (16%) revealed brain anomalies such as schizencephaly and hydranencephaly. One patient was diagnosed with Rett syndrome and one with $M{\ddot{o}}bius$ syndrome. Conclusion: As chromosomal microarray can elucidate the cause of previously unexplained developmental delay, it should be considered as a first-tier cytogenetic diagnostic test for children with unexplained developmental delay.

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.9
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• pp.1573-1595
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• 2011

In this paper, the outage performance of multiuser multiple-input single-output (MISO) systems exploiting joint spatial and multiuser diversities is investigated for Rayleigh fading channels with outdated feedback. First, we derive closed-form exact outage probabilities for the joint diversity schemes that combine user scheduling with different spatial diversity techniques, including: 1) transmit maximum-ratio combining (TMRC); 2) transmit antenna selection (TAS); and 3) orthogonal space-time block coding (OSTBC). Then the asymptotic outage probabilities are analyzed to gain more insights into the effect of feedback delay. It is observed that with outdated feedback, the asymptotic diversity order of the multiuser OSTBC (M-OSTBC) scheme is equal to the number of transmit antennas at the base station, while that of the multiuser TMRC (M-TMRC) and the multiuser TAS (M-TAS) schemes reduce to one. Further by comparing the asymptotic outage probabilities, it is found that the M-TMRC scheme outperforms the M-TAS scheme, and the M-OSTBC scheme can perform best in the outage regime of practical interest when the feedback delay is large. Theoretical analysis is verified by simulation results.