• Journal of Korean Society of Industrial and Systems Engineering
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• v.46 no.2
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• pp.1-12
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• 2023

To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

• IE interfaces
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• v.17 no.1
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• pp.1-12
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• 2004

In a modern semiconductor device manufacturing industry, statistical bin limits on wafer level test bin data are used for minimizing value added to defective product as well as protecting end customers from potential quality and reliability excursion. Most wafer level test bin data show skewed distributions. By Monte Carlo simulation, this paper evaluates methods and sample size effect regarding determination of statistical bin limits. In the simulation, it is assumed that wafer level test bin data follow the Poisson distribution. Hence, typical shapes of the data distribution can be specified in terms of the distribution's parameter. This study examines three different methods; 1) percentile based methodology; 2) data transformation; and 3) Poisson model fitting. The mean square error is adopted as a performance measure for each simulation scenario. Then, a case study is presented. Results show that the percentile and transformation based methods give more stable statistical bin limits associated with the real dataset. However, with highly skewed distributions, the transformation based method should be used with caution in determining statistical bin limits. When the data are well fitted to a certain probability distribution, the model fitting approach can be used in the determination. As for the sample size effect, the mean square error seems to reduce exponentially according to the sample size.

• The Korean Journal of Applied Statistics
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• v.35 no.5
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• pp.593-601
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• 2022

We call "fruad" the cases that are not frequently occurring but cause significant losses. Fraud detection is commonly encountered in various applications, including wafer production in the semiconductor industry. It is not trivial to directly extend the standard binary classification methods to the fraud detection context because the misclassification cost is much higher than the normal class. In this article, we propose the functional fraud detection support vector machine (F²DSVM) that extends the fraud detection support vector machine (FDSVM) to handle functional covariates. The proposed method seeks a classifier for a function predictor that achieves optimal performance while achieving the desired sensitivity level. F²DSVM, like the conventional SVM, has piece-wise linear solution paths, allowing us to develop an efficient algorithm to recover entire solution paths, resulting in significantly improved computational efficiency. Finally, we apply the proposed F²DSVM to the defective wafer detection problem and assess its potential applicability.

• The Korean Journal of Applied Statistics
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• v.35 no.3
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• pp.407-419
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• 2022

The semiconductor fabrication process is complex and time-consuming. There are sometimes errors in the process, which results in defective die on the wafer bin map (WBM). We can detect the faulty WBM by finding some patterns caused by dies. When one manually seeks the failure on WBM, it takes a long time due to the enormous number of WBMs. We suggest a two-step approach to discover the probable pattern on the WBMs in this paper. The first step is to separate the normal WBMs from the defective WBMs. We adapt a hierarchical clustering for de-noising, which nicely performs this work by wisely tuning the number of minimum points and the cutting height. Once declared as a faulty WBM, then it moves to the next step. In the second step, we classify the patterns among the defective WBMs. For this purpose, we extract features from the WBM. Then machine learning algorithm classifies the pattern. We use a real WBM data set (WM-811K) released by Taiwan semiconductor manufacturing company.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.44 no.4
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• pp.128-135
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• 2021

WDM(Wavelength Division Multiplexing) is called a wavelength division multiplexing optical transmission method and is a next-generation optical transmission technology. Case company F has recently developed and sold PLC(Planar Lightwave Circuit), a key element necessary for WDM system production. Although Chinese processing companies are being used as a global outsourcing strategy to increase price competitiveness by lowering manufacturing unit prices, the average defect rate of products manufactured by Chinese processing companies is more than 50%, causing many problems. However, Chinese processing companies are trying to avoid responsibility, saying that the cause of the defect is the defective PLC Wafer provided by Company F. Therefore, in this study, the responsibility of the PLC defect is clearly identified through estimating the defect rate of PLC using the sampling inspection method, and the improvement plan for each cause of the PLC defect for PLC yeild improvement is proposed. The result of this research will greatly contribute to eliminating the controversy over providing the cause of defects between global outsourcing companies and the head office. In addition, it is expected to form a partnership with Company F and a Chinese processing company, which will serve as a cornerstone for successful global outsourcing. In the future, it is necessary to increase the reliability of the PLC yield calculation by extracting more precisely the number of defects.

• Journal of the Optical Society of Korea
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• v.19 no.6
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• pp.687-694
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• 2015

A photoluminescence (PL) imaging method using a vision camera was employed to inspect InGaN/GaN quantum-well light-emitting diode (LED) epi-wafers. The PL image revealed dark spot defective regions (DSDRs) as well as a spatial map of integrated PL intensity of the epi-wafer. The Shockley-Read-Hall (SRH) nonradiative recombination coefficient increased with the size of the DSDRs. The high nonradiative recombination rates of the DSDRs resulted in degradation of the optical properties of the LED chips fabricated at the defective regions. Abnormal current-voltage characteristics with large forward leakages were also observed for LED chips with DSDRs, which could be due to parallel resistances bypassing the junction and/or tunneling through defects in the active region. It was found that the SRH nonradiative recombination process was dominant in the voltage range where the forward leakage by tunneling was observed. The results indicated that the DSDRs observed by PL imaging of LED epi-wafers were high density SRH nonradiative recombination centers which could affect the optical and electrical properties of the LED chips, and PL imaging can be an inspection method for evaluation of the epi-wafers and estimation of properties of the LED chips before fabrication.

• Korean Journal of Materials Research
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• v.20 no.8
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• pp.423-428
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• 2010

This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of a complementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

• Korean Chemical Engineering Research
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• v.51 no.6
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• pp.666-670
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• 2013

Recovery method of silicon wafer from defective products generated from manufacturing process of silicon solar cells was studied. The removal effect of the N layer and antireflection coating (ARC) of the waste solar cell were investigated at room temperature ($25^{\circ}C$) by variation of concentration of $H_3PO_4$, $NH_4HF_2$, and concentration and types of chelating agent. Removal efficiency was the best in the conditions; 10 wt% $H_3PO_4$ 2.0 wt% $NH_4HF_2$, 1.5 wt% Hydantoin. Increasing the concentration of $H_3PO_4$, the surface contamination degree was increased and the thickness of the silicon wafe became thicker than the thickness before surface treatment because of re-adsorption on the silicon wafer surface by electrostatic attraction of the fine particles changed to (+). The etching method by mixed solution of $H_3PO_4$-$NH_4HF_2$-chelating agents was expected to be great as an alternative to conventional RCA cleaning methods and as the recycle method of waste solar cells, because all processes are performed at room temperature, the process is simple, and less wastewater, the removal efficiency of the surface of the solar cell was excellent.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.141-141
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• 2010

The effect of thermal anneal on the characteristics of structural properties and the enhancement of luminescence and photovoltaic (PV) characteristics of silicon-rich silicon-nitride films were investigated. By using an ultra high vacuum ion beam sputtering deposition, B-doped silicon-rich silicon-nitride (SRSN) thin films, with excess silicon content of 15 at. %, on P-doped (n-type) Si substrate was fabricated, sputtering a highly B doped Si wafer with a BN chip by N plasma. In order to examine the influence of thermal anneal, films were then annealed at different temperature up to $1100^{\circ}C$ under $N_2$ environment. Raman, X-ray diffraction, and X-ray photoemission spectroscopy did not show any reliable evidence of amorphous or crystalline Si clusters allowing us concluding that nearly no Si nano-cluster could be formed through the precipitation of excess Si from SRSN matrix during thermal anneal. Instead, results of Fourier transform infrared and X-ray photoemission spectroscopy clearly indicated that defective, amorphous Si-N matrix of films was changed to be well-ordered thanks to high temperature anneal. The measurement of spectral ellipsometry in UV-visible range was carried out and we found that the optical absorption edge of film was shifted to higher energy as the anneal temperature increased as the results of thermal anneal induced formation of $Si_3N_4$-like matrix. These are consistent with the observation that higher visible photoluminescence, which is likely due to the presence of Si-N bonds, from anneals at higher temperature. Based on these films, PV cells were fabricated by the formation of front/back metal electrodes. For all cells, typical I-V characteristic of p-n diode junction was observed. We also tried to measure PV properties using a solar-simulator and confirmed successful operation of PV devices. Carrier transport mechanism depending on anneal temperature and the implication of PV cells based on SRSN films were also discussed.