• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.118-119
• /
• 2009

This paper presents the feature profile evolution silicon deep trench etching, which is very crucial for the commercial wafer process application. The silicon deep trenches were etched with the SF6 gas & Hbr gas based process recipe. The optimized silicon deep trench process resulted in vertical profiles (87o~90o) with loading effect of < 1%. The process recipes were developed for the silicon deep trench etching applications. This scheme provides vertically profiles without notching of top corner was observed. In this study, the production of SF6 gas based silicon deep trench etch process much more strongly than expected on the basis of Hbr gas trench process that have been investigated by scanning electron microscope (SEM). Based on the test results, it is concluded that the silicon deep trench etching shows the sufficient profile for practical MOS FET silicon deep trench technology process.

• Journal of IKEEE
• /
• v.25 no.2
• /
• pp.356-361
• /
• 2021

Super Junction structure is the proposed structure to minimize the Trade-off phenomenon of power devices. Super Junction can have On-resistance(Ron) characteristics as less as five times than conventional structure. There are process methods that Multi-Epi and Deep-Trench of Super Junction structure. The reason for this is that Deep-Trench process is known to be a relatively difficult manufacturing method because it is easy to form a P-Pillar by burying impurities on top of a silicon substrate through a Deep-Trench process. However, the structure created by the Deep-Trench process has low On-resistance and high breakdown voltage, showing better efficiency. In this paper, we suggested a novel method in the process and designed structure with Charge Balance theory.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.88-89
• /
• 2009

In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1996.05a
• /
• pp.64-64
• /
• 1996

• Journal of the Korean Ceramic Society
• /
• v.39 no.6
• /
• pp.570-575
• /
• 2002

The present tendency of electrical and electronics is concentrated on MEMS devices for advantage of miniaturization, intergration, low electric power and low cost. Therefore it is essential that high aspect ratio and high etch rate by HDP technology development, so that silicon deep trench etching reactions was studied by ICP equipment. Deep trench etching of silicon was investigated as function of platen power, etch step time of etch/passivation cycle time and SF$\_$6/:C$_4$F$\_$8/ flow rate. Their effects on etch profile, scallops, etch rate, uniformity and selectivity were also studied.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.14 no.1
• /
• pp.1-5
• /
• 2001

STI(shallow trench isolation)-CMP(chemical mechanical polishing) process have been substituted for LOCOS(local oxidation of silicon) process to obtain global planarization in the below sub-0.5㎛ technology. However TI-CMP process, especially TI-CMP with RIE(reactive ion etching) etch back process, has some kinds of defect like nitride residue, torn oxide defect, etc. In this paper, we studied how to reduced torn oxide defects after STI-CMP with RIE etch back processed. Although torn oxide defects which can occur on trench area is not deep and not severe, torn oxide defects on moat area is not deep and not severe, torn oxide defects on moat area is sometimes very deep and makes the yield loss. Thus, we did test on pattern wafers which go through trench process, APECVD process, and RIE etch back process by using an IPEC 472 polisher, IC1000/SUVA4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the origin of torn oxide defects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.26 no.10
• /
• pp.720-725
• /
• 2013

Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have analyzed trench process, field limit ring process for fabrication of unified trench gate power MOSFET. And we have analyzed electrical characteristics of fabricated unified trench gate power MOSFET. The optimal trench process was based on SF6. After we carried out SEM measurement, we obtained superior trench gate and field limit ring process. And we compared electrical characteristics of planar and trench gate unified power MOSFET after completing device fabrication. As a result, the both of them was obtained 500 V breakdown voltage. However trench gate unified power MOSFET was shown improved Vth and on state voltage drop characteristics than planar gate unified power MOSFET.

• ETRI Journal
• /
• v.35 no.4
• /
• pp.632-637
• /
• 2013

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p-pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p-pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n-drift layer due to the trenched p-pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.4
• /
• pp.270-275
• /
• 2012

Power MOSFET(metal oxide silicon field effect transistor) operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. But on-resistance characteristics depending on the increasing breakdown voltage spikes is a problem. So 600 V planar power MOSFET compare to 1/3 low on-resistance characteristics of super junction MOSFET structure. In this paper design to 600 V planar MOSFET and super junction MOSFET, then improvement of comparative analysis breakdown voltage and resistance characteristics. As a result, super junction MOSFET improve on about 40% on-state voltage drop performance than planar MOSFET.

• Journal of Korean Vacuum Science & Technology
• /
• v.2 no.2
• /
• pp.122-132
• /
• 1998

Characteristics of inductively coupled Cl2/O2 and Cl2/N2 plasmas and their effects on the formation of submicron deep trench etching of single crystal silicon have been investigated using Langmuir probe, quadrupole mass spectrometer (QMS), X-ray photoelectron spectroscopy (XPS), and scanning electron microscopy (SEM), Also, when silicon is etched with oxygen added chlorine plasmas, etch products recombined with oxygen such as SiClxOy emerged and Si-O bondings were found on the etched silicon surface. However, when nitrogen is added to chlorine, no etch products recombined with nitrogen nor Si-N bondings were found on the etched silicon surface. When deep silicon trenches were teached, the characteristics of Cl2/O2 and Cl2/N2 plasmas changed the thickness of the sidewall residue (passivation layer) and the etch profile. Vertical deep submicron trench profiles having the aspect ratio higher than 5 could be obtained by controlling the thickness of the residue formed on the trench sidewall using Cl2(O2/N2) plasmas.