• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.397-409
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• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.3
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• pp.1301-1312
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• 2020

Using decode-and-forward relaying in the cognitive radio networks, the spectrum efficiency can improve furthermore. The optimization algorithm of the spectrum sensing estimation time is presented for the cognitive relay networks in this paper. The longer sensing time will bring two aspects of the consequences. On the one hand, the channel parameters are estimated more accurate so as to reduce the interferences to the authorized users and to improve the throughput of the cognitive users. On the other hand, it shortens the transmission time so as to decease the system throughput. In this time, it exists an optimal sensing time to maximize the throughput. The channel state information of the sub-bands is considered as the exponentially distributed, so a stochastic programming method is proposed to optimize the sensing time for the cognitive relay networks. The computer simulation results using the Matlab software show that the algorithm is effective, which has a certain engineering application value.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• Journal of Communications and Networks
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• v.9 no.3
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• pp.265-273
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• 2007

This paper expands an analytical performance model of 802.11 to accurately estimate throughput and energy demand of 802.11-based wireless sensor network (WSN) when sensor nodes employ Reed-Solomon (RS) codes, one of block forward error correction (FEC) techniques. This model evaluates these two metrics as a function of the channel bit error rate (BER) and the RS symbol size. Since the basic recovery unit of RS codes is a symbol not a bit, the symbol size affects the WSN performance even if each packet carries the same amount of FEC check bits. The larger size is more effective to recover long-lasting error bursts although it increases the computational complexity of encoding and decoding RS codes. For applying the extended model to WSNs, this paper collects traffic traces from a WSN consisting of two TIP50CM sensor nodes and measures its energy consumption for processing RS codes. Based on traces, it approximates WSN channels with Gilbert models. The computational analyses confirm that the adoption of RS codes in 802.11 significantly improves its throughput and energy efficiency of WSNs with a high BER. They also predict that the choice of an appropriate RS symbol size causes a lot of difference in throughput and power waste over short-term durations while the symbol size rarely affects the long-term average of these metrics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.11
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• pp.18-26
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n wireless LAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. From fixed-point modeling and Matlab simulations for various bit-widths, decoding performance and optimal hardware parameters such as fixed-point bit-width are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18-${\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.2
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• pp.363-371
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• 2013

This paper describes a multi-standard LDPC decoder which supports 19 block lengths(576~2304) and 6 code rates(1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6) of IEEE 802.16e mobile WiMAX standard and 3 block lengths(648, 1296, 1944) and 4 code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A DFU(decoding function unit) based on sign-magnitude arithmetic is used for hardware reduction. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.13-${\mu}m$ CMOS cell library. It has 312,000 gates and 70,000 bits RAM. The estimated throughput is about 79~210 Mbps at 100 MHz@1.8v.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.771-777
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• 2010

This paper proposes a new signal detection method, called QR-OSIC with Candidates (QOC) method, for spatially multiplexed multiple input multiple output (MIMO) systems. By using the ordered successive interference cancellation (OSIC) algorithm and the maximum likelihood (ML) metric, the proposed method achieves near-ML performance without requiring a large number of candidates. Although the proposed method can be used for both hard and soft decoding systems, it is especially useful for soft decoding systems since the LLR values for all the bits can be efficiently computed without using LLR estimation. The proposed method is also suitable for VLSI implementation since it leads to fixed throughput system.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.48-58
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• 2016

This paper presents the high-throughput fully-parallel architecture for GF(64) (160,80) regular (2,4) non-binary LDPC (NB-LDPC) codes decoder based on the extended min sum algorithm. We exploit the NB-LDPC code that features a very low check node and variable node degree to reduce the complexity of decoder. This paper designs the fully-parallel architecture and allows the interleaving check node and variable node to increase the throughput of the decoder. We further improve the throughput by the proposed early sorting to reduce the latency of the check node operation. The proposed decoder has the latency of 37 cycles in the one decoding iteration and achieves a high throughput of 1402Mbps at 625MHz.

• The Journal of the Acoustical Society of Korea
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• v.34 no.4
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• pp.295-302
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• 2015

Acoustic channels are characterized by long multipath spreads that cause inter-symbol interference. The way in which this fact influences the design of the receiver structure is considered. To satisfy performance and throughput, we presented consecutive iterative BCJR (Bahl, Cocke, Jelinek, Raviv) equalization to improve the performance and throughput. To achieve low error performance, we resort to powerful BCJR equalization algorithms that iteratively update probabilistic information between inner decoder and outer decoder. Also, to achieve high throughput, we divide long packet into consecutive small packets, and the estimate channel information of previous packets are compensated to next packets. Based on experimental channel response, we confirmed that the performance is improved for long length packet size.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.63-70
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• 2016

To increase throughput efficiency and improve performance, FTN(Faster Than Nyquist) method and LDPC(Low Density Parity Code) codes are employed in DVB-S3 system. In this paper, we proposed efficient turbo equalization model to minimize inter symbol interference induced by FTN transmission. This paper introduces two conventional scheme employing SIC(Successive Interference Cancellation) and BCJR equalizer. Then, we proposed new scheme to resolve problems in this two conventional scheme. To make performance improved in turbo equalization model, the outputs of LDPC and BCJR equalizer are iteratively exchange probabilistic information. In fed LDPC outputs as extrinsic informa tion of BCJR equalizer. we split LDPC output to separate bit probabilities. We compare performance of proposed scheme to that of conventional methods through using simulation in AWGN(Additive White Gaussian Noise) channel. We confirmed that performance was improved compared to conventional methods as increasing throughput parameters of FTN.