• The KIPS Transactions:PartD
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• v.13D no.7 s.110
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• pp.901-908
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• 2006

With the development of wireless communication techniques and mobile environment we are able to transmit data between mobile systems without restriction of time and space. Recently, researches on the data communication between mobile systems have focused on a small amount of sending out or receiving data and data synchronization at a fixed server and mobile clients in mobile environment. However, two more servers should be able to move mutual independently, information is shared with other systems, and data is synchronized in the special environment like a battlefield situation. Therefore, we propose a data synchronization method between systems moving mutual independently in mobile environment. The proposed method is an optimization solution to data propagation path between servers that considers limited bandwidth and process of data for disconnection communication. In addition, we propose a data reduction method that considers importance and sharing of information in order to reduce data transmission between huge servers. We verified the accuracy of data after accomplishing our data synchronization method by applying it in the real world environment. Additionally, we showed that our method could accomplish data synchronization normally within an allowance tolerance when we considered data propagating delay time by server extension.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1334-1342
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• 1997

The future data communications are expected to support the various andcomplex services withmultimedia. So thispaper has focused on the multimedia synchronization problem which has important position in multimedia presentation. Firstly, this paper consider the suitable layer for multimedia synchronization in the communication structure as transport layer or upper ones, in which we propose synchronization mechanism using fixed length buffer with bufer-lever or upper ones, in which we propose synchronization mechanism using fixed length bufer with buffer-level. The proposed mechansim also supports intra-and inter-media synchronization among media. Through simulation, we prove our analysis of the fixed-length buffersize that theproposed mechanism can provide. Also we show comparisons between our mechanism and other scheme.

• Proceedings of the KSRS Conference
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• 2008.10a
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• pp.228-231
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• 2008

For a satellite data communication, the technology of frame synchronization is widely used between a sender and a receiver. Last year, we suggested zero-loss frame synchronization [1] using pattern search and using bits threshold search algorithm that is based on SIMD technology [2,3]. This algorithm could solve both of hardware and software drawbacks, which are frame loss and low processing performance. However, this algorithm didn't optimize the processing of output data, synchronized data, which caused overhead to the memory allocation and the memory copy. Consequently, the performance of the frame synchronizer application was degraded. In this paper, we enhance previous work using a circular buffer in order to optimize the output data processing. The performance comparison with the previous algorithm shows that the enhanced proposed approach dramatically outperforms in the output data processing speed.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.123-134
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• 2004

The synchronized clock performance in the synchronization network and SDH transmission network design is an important element in aspect of guaranteeing network stability and data transmission. Consequently the simulator which can applicable various parameters and several input levels from the best state to the worst state for performance analysis of the synchronized clock is required in case of network design. Therefore, in this paper, 1 developed the SNCA and TNCA for analysis of the synchronized clock in the synchronization network and transmission network. And utilizing these simulators with various wander generation, node number and clock state, 1 obtained the synchronized clock characteristics and maximum network nodes In NE1, NE2 and NE3 transmission network and DOTS1, DOTS2 synchronization network.

• Journal of Advanced Navigation Technology
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• v.24 no.4
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• pp.285-290
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• 2020

This paper presents a time synchronization algorithm based on PLL for application to telemetry systems and implement FPGA logic. The large aircraft of the telemetry system acquires status information through each distributed acquisition devices and analyzes the flight status in real time. For this reason, time synchronization between systems is important to improve precision. This paper presents a PLL based time synchronization algorithm that is less complex than other time synchronization methods and takes less time to process data because there is minimized message transmission for synchronization. The validity of proposed algorithm is proved by simulation of Python. And the VHDL logic was implemented in FPGA to check the time synchronization performance.

• Journal of IKEEE
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• v.23 no.3
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• pp.1096-1099
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• 2019

In this paper, we propose the protocol for construction of smart factory. The proposed protocol for construction of smart factory consists of an OPC UA Server/Client, a technology of TSN realtime communication, a NTP & PTP time synchronization protocol, a FieldBus protocol and conversion module, a technology of saving data for data transmit latency and synchronization protocol. OPC UA server/client is a system integration protocol which makes interface industrial hardware device and supports standardization which allows in all around area and also in not independent from any platform. A technology of TSN realtime communication provides an high sensitive time management and control technology in a way of sharing specific time between devices in the field of high speed network. NTP & PTP time synchronization protocol supports IEEE1588 standardization. A fieldbus protocol and conversion module provide an extendable connectivity by converting industrial protocol to OPC. A technology of saving data for data transmit latency and synchronization protocol provide a resolution function for a loss and latency of data. Results from testing agencies to assess the performance of proposed protocol for construction of smart factory, response time was 0.1367ms, synchronization time was 0.404ms, quantity of concurrent access was 100ea, quantity of interacting protocol was 5ea, data saving and synchronization was 1,000 nodes. It produced the same result as the world's highest level.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.177-178
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• 2005

Wireless 1394 over IEEE802.15.3 must allow a data reserved for delivery over a wired 1394 network to be delivered over an IEEE802.15.3 wireless network through bridging IEEE 1394 to IEEE802.15.3. Isochronous transfers on the 1394 bus guarantee timely delivery of data. Specifically, isochronous transfers are scheduled by the bus so that they occur once every $125\;{\mu}s$ and require clock time synchronization to complete the real-time data transfer. IEEE1394.1 and Protocol Adaptation Layer for IEEE1394 over IEEE802.15.3 specify clock time synchronization for a wired 1394 bus network to a wired 1394 bus network and wireless 1394 nodes, which are IEEE802.15.3 nodes handling 1394 applications, over IEEE802.15.3. Thus, the clock time synchronizations are just defined within a homogeneous network environment like IEEE1394 or IEEE802.15.3 until now. This paper proposes new clock time synchronization method for wireless 1394 heterogeneous networks between 1394 and 802.15.3. If new method is adopted for various wireless 1394 products, consumer electronics devices such as DTV and Set-top Box or PC devices on a 1394 bus network can transmit real time data to the AV devices on the other 1394 bus in a different place via IEEE 802.15.3.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.787-795
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• 1994

In this paper, we have proposed a bit synchronization algorithm which extracts the synchronized clock for random NRZ signal and designed a circuit followed by its performance analysis. The synchronization circuit consists of the Data Transition Detector and Mod 64 Counter, Phase Comparison and Controller, 64 Divider. The data input rate and master clock rate are 16 Kbps and 4.096MHz, respectively. The phase is compensated by 1/64 of the data signal period for every data bit. Through a series of experiments, the maximum immunity of phase jiter for input signal and the deviation of the recovered clock are measured 23.8% and 1.6%, respectively. The fully digital synchronization circuit is simple to implement into signal IC chip and also effective for the low speed digital mobile communications.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.22 no.6
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• pp.1363-1374
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• 2012

The number and use of Internet connected devices has dramatically increased in the last several years. Therefore many services synchronizing data in real-time is increasing such as mail, calendar and storage service. This service provides convenience to users. However, after devices are seized, the data could be changed because of characteristic about real-time synchronization. Therefore digital investigation could be difficult by this service. This work investigates the traces on each local device and proposes a method for the preservation of real-time synchronized data. Based on these, we propose the procedures of real-time synchronization data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.99-108
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• 1999

In this paper, we propose $\pi$/4 QPSK scheme with block modulation algorithm, which can reduce preamble in order to transmit ATM cell efficiently in the uplink channel of LMDS, and also designed a new carrier recovery circuit which can improve carrier synchronization performance of block demodulation algorithm. The $\pi$/4 QPSK scheme employing the proposed block modulation algorithm achieved efficient frame transmission by making use of a few preamble when carrier synchronization, symbol timing synchronization and slot timing synchronization were performed by burst data of ATM cell in LMDS environment. For performance evaluation of the proposed method, a simulation analyzing the variation of carrier synchronization, symbol timing synchronization and slot timing synchronization using LMDS environment and burst mode condition was executed. In the simulation, the proposed method showed a good performance even though the reduced preamble as a few aspossible when carrier synchronization, symbol timing synchronization and slot timing synchronization is performed.