• Journal of Korean Society on Water Environment
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• v.25 no.3
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• pp.351-362
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• 2009

The Soil and Water Assessment Tool (SWAT) model, semi-distributed model, first divides the watershed into multiple subwatersheds, and then extracts the basic computation element, called the Hydrologic Response Unit (HRU). In the process of HRU generation, the spatial information of land use and soil maps within each subwatershed is lost. The SWAT model estimates the HRU topographic data based on the average slope of each subwatershed, and then use this topographic datum for all HRUs within the subwatershed. To improve the SWAT capabilities for various watershed scenarios, the Spatially Distributed-HRU (SD-HRU) pre-processor module was developed in this study to simulate site-specific topographic data. The SD-HRU was applied to the Hae-an watershed, where field slope lengths and slopes are measured for all agricultural fields. The analysis revealed that the SD-HRU pre-processor module needs to be applied in SWAT sediment simulation for accurate analysis of soil erosion and sediment behaviors. If the SD-HRU pre-processor module is not applied in SWAT runs, the other SWAT factors may be over or under estimated, resulting in errors in physical and empirical computation modules although the SWAT estimated flow and sediment values match the measured data reasonably well.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.87-94
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• 2003

In this paper, we propose an IFFT/FFT design method to minimize quantization error in IEEE 802.11a WLAN. In the proposed algorithm, the twiddle coefficient of IFFT/FFT processor is manipulated by the statistics distribution of the input data at each stage. We applies this algorithm to radix-2/$^2$ SDF architecture. Both IFFT and FFT processor shares the circuit blocks cause to the symmetric architecture. The maximum quantization error with the 10 bits length of the input and output data is 0.0021 in IFFT and FFT that has a self-loop structure with the proposed method. As a result, the proposed architecture saves 3bits for the data to keep the same resolution compared with the conventional method.

• The Transactions of the Korea Information Processing Society
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• v.6 no.6
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• pp.1419-1432
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• 1999

The Document Management System(DMS) is a system which retrieves and manages library information efficiently. Since DMS manages the information using only one table, it does not need to provide join and view operations that spend high cost in traditional DBMS. In addition, DMs requires new operations because of their property. the operation has not been supported in existing DBMSs. In this paper we define a data language which represents the structure definition and process of data on the DMS. Especially we define Ranking and Proximity operation which is needed in Document Retrieval,. We also design and implement a query processor to process the query constructed with the data language. When the exiting query processors of relational DBMS are used as a query processor of DMS, they degrade the whole system performance. The proposed query processor not only overcomes such a problem but also supports new operation which is needed in DMS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.420-435
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• 2001

As multimedia technology has rapidly grown recently, many researches to process multimedia data efficiently using general-purpose processors have been studied. In this paper, we proposed multimedia instructions which can process multimedia data effectively, and suggested a processor architecture for those instructions. The processor was described with Verilog-HDL in the behavioral level and simulated with CADENCE$^{TM}$ tool. Proposed multimedia instructions are total 48 instructions which can be classified into 7 groups. Multimedia data have 64-bit format and are processed as parallel subwords of 8-bit 8 bytes, 16-bit 4 half words or 32-bit 2 words. Modeled processor is developed based on the Integer Unit of SPARC V.9. It has five-stage pipeline RISC architecture with Harvard principle.e.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1201-1210
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• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• Proceedings of the KIEE Conference
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• 2001.07a
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• pp.237-239
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• 2001

This paper describes the digital relay simulator system using digital signal processor. The simulator system has two parts, one is software and the other is hardware part. The simulation software has variety calculation engines ; EMTP simulation data file conversion, user define simulation data generation, sequence data generation, data analysis engines. etc, these are designed upon GUI. And simulator software provides easy control interface for users, the simulator software performs on every MS Windows OS. The simulator hardware design uses 32bit floating point DSP(TMS320C32) architecture to achieve flexibility and high speed operation.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.96-105
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• 1992

The use of fixed-point digital signal processors, such as the TMS 320C25, requires scaling of data at each arithmetic step to prevent overflows while keeping the accuracy. A software which automatizes this process is developed for TMS 320C25. The programmers use a model of a hypothetical floating-point digital signal processor and a floating-point format for data representation. However, the program and data are automatically translated to a fixed-point version by this software. Thus, the execution speed is not sacrificed. A fixed-point variable has a unique binary-point location, which is dependent on the range of the variable. The range is estimated from the floating-point simulation. The number of shifts needed for arithmetic or data transfer step is determined by the binary-points of the variables associated with the operation. A fixed-point code generator is also developed by using the proposed automatic scaling software. This code generator produces floating-point assembly programs from the specifiations of FIR, IIR, and adaptive transversal filters, then floating-point programs are transformed to fixed-point versions by the automatic scaling software.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.99-108
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• 2011

Processor technology is currently continued to parallel processing techniques, not by only increasing clock frequency of a single processor due to the high technology cost and power consumption. In this paper, a SIMD (Single Instruction Multiple Data) based parallel processor is introduced that efficiently processes massive data inherent in multimedia. In addition, this paper proposes pixel subword parallel processing instructions for the SIMD parallel processor architecture that efficiently operate on the image and video pixels. The proposed pixel subword parallel processing instructions store and process four 8-bit pixels on the partitioned four 12-bit registers in a 48-bit datapath architecture. This solves the overflow problem inherent in existing multimedia extensions and reduces the use of many packing/unpacking instructions. Experimental results using the same SIMD-based parallel processor architecture indicate that the proposed pixel subword parallel processing instructions achieve a speedup of $2.3{\times}$ over the baseline SIMD array performance. This is in contrast to MMX-type instructions (a representative Intel multimedia extension), which achieve a speedup of only $1.4{\times}$ over the same baseline SIMD array performance. In addition, the proposed instructions achieve $2.5{\times}$ better energy efficiency than the baseline program, while MMX-type instructions achieve only $1.8{\times}$ better energy efficiency than the baseline program.

• The Journal of the Acoustical Society of Korea
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• v.29 no.3
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• pp.191-199
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• 2010

Physical modeling is a synthesis method of high quality sound which is similar to real sound for musical instruments. However, since physical modeling requires a lot of parameters to synthesize sound of a musical instrument, it prevents real-time processing for the musical instrument which supports a large number of sounds simultaneously. To solve this problem, this paper proposes a single instruction multiple data (SIMD) parallel processor that supports real-time processing of sound synthesis of guitar, a representative plucked string musical instrument. To control six strings of guitar, we used a SIMD parallel processor which consists of six processing elements (PEs). Each PE supports modeling of the corresponding string. The proposed SIMD processor can generate synthesized sounds of six strings simultaneously when a parallel synthesis algorithm receives excitation signals and parameters of each string as an input. Experimental results using a sampling rate 44.1 kHz and 16 bits quantization indicate that synthesis sounds using the proposed parallel processor were very similar to original sound. In addition, the proposed parallel processor outperforms commercial TI's TMS320C6416 in terms of execution time (8.9x better) and energy efficiency (39.8x better).

• Korean Journal of Remote Sensing
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• v.20 no.1
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• pp.47-55
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• 2004

We have constructed a level-1 processor to generate brightness temperatures using the direct-broadcast data from the passive microwave radiometer onboard Aqua satellite. Although 50-minute half-orbit data, called a granule, are being routinely produced by global data centers, to our knowledge, this is the first attempt to process 10-minute long direct-broadcast (DB) data. We found that the processor designed for a granule needs modification to apply to the DB data. The modification includes the correction to path number, the selection of land mask and the manipulation of dummy scans. Pixel-to-pixel comparison with a reference indicates the difference in brightness temperature of about 0.2 K rms and less than 0.05 K mean. The difference comes from the different length of data between 50-minute granule and about 10-minute DB data. In detail, due to the short data length, DB data do not always have correct cold sky mirror count. The DB processing system is automated to enable the near-real time generation of brightness temperatures within 5 minutes after downlink. Through this work, we would be able to enhance the use of AMSR-E data, thus serving the objective of direct-broadcast.