• 한국전기전자재료학회논문지
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• 제11권1호
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

• 한국산학기술학회논문지
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• 제7권3호
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• pp.344-349
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• 2006

[ $60{\sim}70nm$ ] 급의 design rule을 가진 고집적 반도체 소자를 제작하려면, 트랜지스터 형성 이후의 공정에서 thermal budget을 줄이기 위하여 공정의 온도를 낮추는 것이 중요하다. 본 연구에서는 고온의 습식 산화막을 대체할 수 있는 저온의 LPCVD (Low-Pressure Chemical Vapor Deposition) $SiO_2$(LTO : Low-Temperature Oxide) 박막 증착공정을 제시하였으며, ONO (Oxide/Nitride/Oxide) 구조의 커패시터를 형성하여 증착된 LTO 박막의 전기적인 신뢰성을 평가하였다. LTO 박막은 5 MV/cm 이하의 전기장 영역에서는 고온의 습식 산화막과 크게 차이가 없는 누설전류 특성을 보였으나, 더 높은 전기장의 영역에서는 훨씬 더 우수함을 보여주었다.

• 대한전자공학회논문지SD
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• 제41권10호
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• pp.31-39
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• 2004

이 논문은 파워 잡음 특성이 칩(chip)의 코아 동작에 따라 DDR DRAM용 모듈(Module)과 패키지(package)의 종류의 영향을 받는 다는 것을 보여주고 있다. 이를 분석하기 위해 상용 TSOP-based DIMM 과 FBGA-based DIMM에서 FBGA와 TSOP 패키지형 DRAM 칩을 가지고 임피던스 모양과 파워 잡음을 분석하였다. 일반적인 상식과 달리, FBGA 패키지의 잡음 격리 특성이 TSOP 패키지의 잡음 격리 특성보다 전달되는 잡음에 더 약하고 민감하다는 것이 발견되었다. 또한 자체 및 전달 잡음 특성을 조절하는데 있어서는 모듈상의 디커풀링 커패시터(decoupling capacitors)들 위치가 패키지 자체의 리드선 인덕턴스(lead inductance)보다 더 중요하다는 것을 또한 시뮬레이션 결과들은 보여준다. 따라서 잡음 억제나 잡음 전달로부터 격리의 목표설정 값을 만족시키는 것은 패키지 형태 뿐 아니라 모듈 전체를 고려한 파워 분배 시스템의 설계를 통해서만 얻어질수 있다.

• 한국정보통신학회논문지
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• 제6권5호
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• pp.696-702
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• 2002

RF magnetron reactive sputtering 법으로 BST(Bal-xSrxTiO$_3$)(50/50) 박막을 제작하여, 박막의 결정화 특성 및 표면상태와 함께 박막의 두께에 따른 전기적 특성을 조사하였다. XRD와 AFM을 이용하여 BST 박막의 결정화 특성과 표면상태를 관찰한 결과, 80$0^{\circ}C$ 에서 2분간 후열처리한 박막은 완전한 perovskite 구조를 가지며 표면거칠기도 16.1$\AA$으로 양호한 값을 나타내었다. 박막의 두께가 80nm에서 240nm으로 증가함에 따라 10KHz에서 비유전률은 199에서 265로 증가하였고, 250㎸/cm의 전기장에서 누설 전류밀도는 $0.779 {\mu}m/{cm^2}에서 0.184 {\mu}A/{cm^2}$으로 감소하였다. 두께 240nm인 BST 박막의 경우, 5V에서의 전하축적 밀도와 누설전류밀도는 각각 50.5 $fC/{{\mu}m^2} 와 0.182 {\mu}A/{cm^2}$로, 이는 DRAM의 캐패시터 절연막 응용에 매우 유망한 물질임을 나타내는 결과이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.2
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• pp.1296-1299
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• 2004

MIM capacitor has been investigated for the next generation DRAM. Conventional poly-Si bottom electrode cannot satisfy the requirement of electrical properties and comparability to the high k materials. New bottom electrode material such as ruthenium has been suggested in the fabrication of MIM structure capacitor. However, the ruthenium has to be planarized due to the backend scalability. For the planarization CMP has been widely used in the manufacture of integrated circuit. In this research, ruthenium thin film was Polished by CMP with cerium ammonium nitrate (CAN)base slurry. HNO3 was added on the CAN solution as an additive. In the various concentration of chemical and alumina abrasive, ruthenium surface was etched and polished. After static etching and polishing, etching and removal rate was investigated. Also microroughness of surface was observed by AFM. The etching and removal rate depended on the concentration of CAN, and HNO3 accelerated the etching and polishing of ruthenium. The reasonable removal rate and microroughness of surface was achieved in the 1wt% alumina slurry.

• Transactions on Electrical and Electronic Materials
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• 제1권4호
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• pp.30-39
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• 2000

The variation of electrical properties of (Ba, Sr)TiO$_3$[BST] thin films deposited of RuO$_2$electrode with (Ba+Sr)/Tr ration was investigated. BST thin films with various (Ba+Sr)/Tr ration were deposited on RuO$_2$/Si substrates using in-situ RF magnetron sputtering. It was found that the electrical properties of BST films depends on the composition in the film. The dielectric constant of the BST films is about 190 at the (Ba+Sr)/Tr ration of 1.0, 1,025 and does not change markedly. But , the dielectric constant degraded to 145 as the (Ba+Sr)/Tr ratio increase to 1.0. In particular, the leakage current mechanism of the films shows the strong dependence on the (Ba+Sr)/Tr ration in the films. At the ration (Ba+Sr)/Tr=1,025, the Al/BST/RuO$_2$ capacitor show the most asymmetric behavior in the leakage current density, vs, electric field plot. It is considered that the leakage current of the (Ba+Sr)/Tr=1,025 thin films is controlled by the battier-Iimited process, i,e, Schottky emission.

• 한국결정학회지
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• 제16권2호
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• pp.89-101
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• 2005

Among many material processing related issues for successful scaling down of devices for the next 10 years or so, the advanced gate stack and interconnect technology are two most critical research areas, which need technical innovation. The introduction of new metallic films and appropriate processing technologies are required more than ever. Especially, as the device downscaling continues well into sub 50 nm regime, the paradigm for metal nano film deposition technique research has been shifted to high conformality, low growth temperature, high quality with uniformity at large area wafers. Regarding these, ALD has sparked a lot of interests for a number of reasons. The process is intrinsically atomic in nature, resulting in the controlled deposition of films in sub-monolayer units with excellent conformality. In this paper, the overview on the current issues and the future trends in device processing technologies related to metal nano films as well as the R&D trends in these applications will be discussed. The focus will be on the applications for metal gate, capacitor electrode for DRAM, and diffusion barriers/seed layers for Cu interconnect technology.

• 한국세라믹학회지
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• 제32권4호
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• pp.441-447
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• 1995

Ba0.65Sr0.35TiO3 (BST) thin films were deposited on Pt/SiO2/Si(100) substrate by rf magnetron sputtering. The substrate temperature changed from 35$0^{\circ}C$ to 55$0^{\circ}C$ and crystalline BST thin films were deposited above 45$0^{\circ}C$. Most of the films had (111) preferred orientation regardless of deposition temperature, but the films changed to (100) preferred orientation as gas pressure increased. The dielectric constant increased with increasing substrate temperature and film thickness, and ranged from 100 to 600 at room temperature. The leakage current increased as substrate temperature increased or as film thickness decreased.

• 한국진공학회지
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• 제4권S1호
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• pp.145-150
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• 1995

PZT thin films were fabricated on Pt/Ti/SiO2/Si substrates at $500^{\circ}C$ by ECR-PECVD for the application to the charge storage capacitor of ULSI DRAMs. Perovskite single phase PZT films were obtained by controling the film compositional ratio Pb/(Zr+Ti) close to 1. The anion concentrations in the PZT films were successfully controlled by adjusting the flow rates of each MO sources. Capacitance of a typical 94 nm thick PZT film prepared at $500^{\circ}C$ in this work was about 5.3 uF/$\textrm{cm}^2$, which corresponds to the equivalent SiO2 thickness of 0.65nm.