• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.1
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• pp.33-40
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• 1998

The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

• Journal of the Semiconductor & Display Technology
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• v.19 no.3
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• pp.118-123
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• 2020

In this paper, the design method of asynchronous nonvolatile memory module that can efficiently process and store large amounts of data without loss when the power turned off is proposed and implemented. PSRAM, which takes advantage of DRAM and SRAM, was used for data processing, and NAND flash memory was used for data storage and backup. The problem of a lot of signal interference due to the characteristics of memory devices was solved through PCB design using high-density integration technology. In addition, a boost circuit using the super capacitor of 0.47F was designed to supply sufficient power to the system during the time to back up data when the power is off. As a result, an asynchronous nonvolatile memory module was designed and implemented that guarantees reliability and stability and can semi-permanently store data for about 10 years. The proposed method solved the problem of frequent data loss in industrial sites and presented the possibility of commercialization by providing convenience to users and managers.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.3
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• pp.344-349
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• 2006

The low-temperature processing is very important for fabrication of the very large scale ($60{\sim}70nm$) semiconductor devices since the submicron transistors are sensitive to the thermal budget. Hence, in this work, we propose a noble low-temperature LPCVD (Low-Pressure Chemical Vapor Deposition) process for the $SiO_2$ film and evaluate the electrical reliability of the LTO (Low-Temperature Oxide) by making the capacitors with ONO (Oxide/Nitride/Oxide) structure. The leak current of the LTO was similar to that of the high-temperature wet oxide until the electric field was lower than 5 MV/cm. However, when the electric field was higher, the LTO showed much better characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.31-39
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• 2004

This paper illustrates the noise characteristics under chip's core operations according to types of packages and modules for DDR DRAM For analyzing this, the impedance profiles and power noises are analyzed with DRAM chips having commercial TSOP package and commercial FBGA package on TSOP-based DIMM and FBGA-based DIMH In controversy with common concepts, we find that the noise-isolation characteristics of FBGA package are more weak and sensitive on transferred noises than those of the TSOP package. In addition, the simulated results show that the decoupling capacitor locations of modules are more important to control the self and transfer noise characteristics than the lead inductance of the packages. Therefore, satisfying the target spec of the noise suppression and isolation can be achieved through the design of power distribution systems only with considering not only the package types but also the whole module system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.696-702
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• 2002

The BST $({Bal-xSrxTiO_3})$ (50/50) thin film has been grown by RF magnetron reactive sputtering and its characteristics such as crystallization, surface roughness, and electrical properties have been investigated with varying the film thickness. The crystallization and surface roughness of BST thin film are investigated by using XRD and AFM, respectively. The BST thin film annealed at $800^{\circ}C$ for 2 min has pure perovskite structure and good surface roughness of 16.1$\AA$. As the film thickness increases from 80 nm to 240 nm, the dielectric constant at 10 KHz increases from 199 to 265 and the leakage current density at 250 ㎸/cm decreases from $0.779 {\mu}A/{cm^2} to 0.184 {\mu}A/{cm^2}$. In the case of 240 nm-thick BST thin film, the charge storage density and leakage current density at 5V are 50.5 fC/${{\mu}m^2} and 0.182 {\mu}A/{cm^2}$, respectively. The values indicate that the BST thin film is a very useful dielectric material for the DRAM capacitor.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1296-1299
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• 2004

MIM capacitor has been investigated for the next generation DRAM. Conventional poly-Si bottom electrode cannot satisfy the requirement of electrical properties and comparability to the high k materials. New bottom electrode material such as ruthenium has been suggested in the fabrication of MIM structure capacitor. However, the ruthenium has to be planarized due to the backend scalability. For the planarization CMP has been widely used in the manufacture of integrated circuit. In this research, ruthenium thin film was Polished by CMP with cerium ammonium nitrate (CAN)base slurry. HNO3 was added on the CAN solution as an additive. In the various concentration of chemical and alumina abrasive, ruthenium surface was etched and polished. After static etching and polishing, etching and removal rate was investigated. Also microroughness of surface was observed by AFM. The etching and removal rate depended on the concentration of CAN, and HNO3 accelerated the etching and polishing of ruthenium. The reasonable removal rate and microroughness of surface was achieved in the 1wt% alumina slurry.

• Transactions on Electrical and Electronic Materials
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• v.1 no.4
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• pp.30-39
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• 2000

The variation of electrical properties of (Ba, Sr)TiO$_3$[BST] thin films deposited of RuO$_2$electrode with (Ba+Sr)/Tr ration was investigated. BST thin films with various (Ba+Sr)/Tr ration were deposited on RuO$_2$/Si substrates using in-situ RF magnetron sputtering. It was found that the electrical properties of BST films depends on the composition in the film. The dielectric constant of the BST films is about 190 at the (Ba+Sr)/Tr ration of 1.0, 1,025 and does not change markedly. But , the dielectric constant degraded to 145 as the (Ba+Sr)/Tr ratio increase to 1.0. In particular, the leakage current mechanism of the films shows the strong dependence on the (Ba+Sr)/Tr ration in the films. At the ration (Ba+Sr)/Tr=1,025, the Al/BST/RuO$_2$ capacitor show the most asymmetric behavior in the leakage current density, vs, electric field plot. It is considered that the leakage current of the (Ba+Sr)/Tr=1,025 thin films is controlled by the battier-Iimited process, i,e, Schottky emission.

• Korean Journal of Crystallography
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• v.16 no.2
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• pp.89-101
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• 2005

Among many material processing related issues for successful scaling down of devices for the next 10 years or so, the advanced gate stack and interconnect technology are two most critical research areas, which need technical innovation. The introduction of new metallic films and appropriate processing technologies are required more than ever. Especially, as the device downscaling continues well into sub 50 nm regime, the paradigm for metal nano film deposition technique research has been shifted to high conformality, low growth temperature, high quality with uniformity at large area wafers. Regarding these, ALD has sparked a lot of interests for a number of reasons. The process is intrinsically atomic in nature, resulting in the controlled deposition of films in sub-monolayer units with excellent conformality. In this paper, the overview on the current issues and the future trends in device processing technologies related to metal nano films as well as the R&D trends in these applications will be discussed. The focus will be on the applications for metal gate, capacitor electrode for DRAM, and diffusion barriers/seed layers for Cu interconnect technology.

• Journal of the Korean Ceramic Society
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• v.32 no.4
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• pp.441-447
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• 1995

Ba0.65Sr0.35TiO3 (BST) thin films were deposited on Pt/SiO2/Si(100) substrate by rf magnetron sputtering. The substrate temperature changed from 35$0^{\circ}C$ to 55$0^{\circ}C$ and crystalline BST thin films were deposited above 45$0^{\circ}C$. Most of the films had (111) preferred orientation regardless of deposition temperature, but the films changed to (100) preferred orientation as gas pressure increased. The dielectric constant increased with increasing substrate temperature and film thickness, and ranged from 100 to 600 at room temperature. The leakage current increased as substrate temperature increased or as film thickness decreased.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.145-150
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• 1995

PZT thin films were fabricated on Pt/Ti/SiO2/Si substrates at $500^{\circ}C$ by ECR-PECVD for the application to the charge storage capacitor of ULSI DRAMs. Perovskite single phase PZT films were obtained by controling the film compositional ratio Pb/(Zr+Ti) close to 1. The anion concentrations in the PZT films were successfully controlled by adjusting the flow rates of each MO sources. Capacitance of a typical 94 nm thick PZT film prepared at $500^{\circ}C$ in this work was about 5.3 uF/$\textrm{cm}^2$, which corresponds to the equivalent SiO2 thickness of 0.65nm.