• 전기학회논문지
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• 제65권3호
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• pp.419-427
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• 2016

This paper proposes a design method of LCL-filter for a grid-connected three-phase inverter using a discontinuous PWM (DPWM) method. When using a DPWM method, many harmonic voltages are generated in the inverter output compared to a continuous PWM (CPWM) method. Therefore, an optimized grid-connected filter design is required for a DPWM method. The proposed design method provides generalized formula to design accurate LCL-filter without trial and error procedures. An inverter side inductance is designed by analyzing the current ripple injected to the grid. The Optimized parameters of LCL-filter can be designed by analyzing the total harmonic distortion (THD) and the ripple attenuation factor of the output current. The proposed LCL filter design method is demonstrated by simulation and experimental results.

• Journal of international Conference on Electrical Machines and Systems
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• 제3권4호
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• pp.433-445
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• 2014

Single phase voltage source converter (VSC) is an important power electronic converter (PEC), including single-phase voltage source inverter (VSI), single-phase voltage source rectifier (VSR), single-phase active power filter (APF) and single-phase grid-connection inverter (GCI). As the fundamental part of large scale PECs, single-phase VSC has a wide range of applications. In the paper, as first, on the basis of the concept of the discontinuous pulse-width modulation (DPWM) for three-phase VSC, a new DPWM of single-phase VSR is presented by means of zero-sequence component injection. Then, the transformation from stationary frame (abc) to rotating frame (dq) is designed after reconstructing the other orthogonal current by means of one order all-pass filter. Finally, the presented DPWM based single-phase VSR is established analyzed and simulated by means of MATLAB/SIMULINK. In addition, the DPWMs presented by D. Grahame Holmes and Thomas Lipo are discussed and simulated in brief. Obviously, the presented DPWM can also be used for single-phase VSI, GCI and APF. The simulation results show the validation of the above modulation algorithm, and the DPWM based single-phase VSR has reduced power loss and increased efficiency.

• Journal of Power Electronics
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• 제12권1호
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• pp.98-103
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• 2012

This paper presents a digital pulse width modulator (DPWM) with a reduced digital modulation delay (a transport delay of the modulator) during the transient response of power converters. During the transient response operation of a power converter, as a result of dynamic variations such as load step-up or step-down, the closed loop controller will continuously adjust the duty cycle in order to regulate the output voltage. The larger the modulation delays, the larger the undesired output voltage deviation from the reference point. The three conventional DPWM techniques exhibit significant leading-edge and/or trailing-edge modulation delays. The DPWM technique proposed in this paper, which results in modulation delay reductions, is discussed, experimentally tested and compared with conventional modulation techniques.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.249-250
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• 2006

In this paper, hardware design and implementation of digital controller for the High Precision Digital Power Supply (HPDPS) based on Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA) is presented. Developed digital controller is composed of high resolution Digital Pulse Width Modulation (DPWM) and high resolution analog to digital converter circuit with anti-aliasing filter. And Digital Signal Processor (DSP) has the capability of a few micro-second calculation time for one feedback loop. 32-bit DSP and DPWM with 150[ps] step resolution is used to implement the HPDPS. Also 18-bit 2 mega sample per second ADC board is adopted for the developed digital controller. Also, hardware structure of the developed digital controller and experimental results of the first prototype board for HPDPS is described.

• Journal of Power Electronics
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• 제17권6호
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• pp.1490-1499
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• 2017

The modular multilevel converter (MMC) is generally considered to be a promising topology for medium-voltage and high-voltage applications. However, in order to apply it to high-power applications, a huge number of switching devices is essential. The numerous switching devices lead to considerable switching losses, high cost and a larger heat sink for each of the switching device. In order to reduce the switching losses of a MMC, this paper analyzes the performance of the conventional discontinuous pulse-width modulation (DPWM) method and its efficiency. In addition, it proposes a modified novel DPWM method for advanced switching losses reduction. The novel DPWM scheme includes an additional rotation method for voltage-balancing and power distribution among sub modules (SMs). Simulation and experimental results verify the effectiveness and performance of the proposed modulation method in terms of its switching losses reduction capability.

• 전자공학회논문지
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• 제50권1호
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• pp.148-156
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• 2013

본 논문에서는 디지털 제어부를 공유하며, 회로 동작시간의 분배 방식을 통해 다중 출력을 지원하는 SMPS를 제안한다. 제안된 회로는 Pseudo Relaxation Oscillating 기법의 DPWM 발생기를 사용한다. 제안된 SMPS는 회로의 동작시간 분배 방식을 사용하여 기존의 DPWM 발생기에서 문제가 되는 큰 면적의 디지털 로직 컨트롤러를 공유하는 형태이기 때문에 칩 면적과 효율 측면에서 큰 이점을 가지지만, 각 DPWM 발생기의 실시간 제어가 어려우며 불안정한 출력 전압을 공급할 수 있다는 단점을 가진다. 이를 해결하기 위해 본 논문에서는 동작시간 분배 방식으로 인해 동작클록이 인가되지 않은 DPWM 발생기들의 출력전압을 실시간으로 피드백 받아 안정된 출력 전압을 공급할 수 있는 실시간 전류 보정 기법을 제안한다. 제안된 SMPS를 100MHz의 내부 제어 동작 주파수와 10MHz 스위칭 주파수로 동작시킬 시, 소모되는 내부 코어 회로의 최대 전류는 4.9mA이며, 출력 버퍼를 포함한 전체 시스템의 전력 소모는 30mA이다. 또한 800mA, 100KHz의 load current regulation 조건으로 시뮬레이션 시, 3.3V 출력전압에 대한 최대 리플 전압은 11mV, Over/Undershoot voltage는 각각 10mV, 19.6mV 이다. 코어 회로의 크기는 $700{\mu}m{\times}800{\mu}m$의 작은 면적으로 구현가능하다. 제안된 회로는 Dong-bu Hitek BCD $0.35{\mu}m$ 공정을 이용한 시뮬레이션을 통해 검증되었다.

• 한국철도학회논문집
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• 제20권4호
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• pp.448-457
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• 2017

본 논문에서는 불연속 변조 기법을 이용한 고속철도 추진제어장치용 단상 PWM 컨버터에 대해 연구하였다. 기존 PWM 컨버터는 대 전력 특성으로 인해 스위칭 손실을 줄이기 위해 주파수 변조지수를 10 이하로 낮게 사용함에 따라 제어의 대역폭이 감소하고, 안정적인 역률 제어를 위해 추가의 보상 기법을 필요로 하는 등의 문제점을 가지고 있다. 이를 해결하기 위해 3상 PWM 인버터에서 사용하는 불연속 변조 기법을 단상 PWM 컨버터에 적용하였다. 제안한 방식은 옵셋 전압 기법을 활용하여 간단히 구현될 수 있으며 동일 스위칭 손실 대비 주파수 변조 지수를 2배 증가시켜 제어 특성을 향상시키고 스위치 간의 동특성도 동일하게 가져갈 수 있다. 100 kW급 PWM 컨버터에 대한 시뮬레이션을 통해 제안한 불연속 변조 기법에 대한 타당성을 검증하였다.

• Journal of Power Electronics
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• 제17권3호
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• pp.686-694
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• 2017

Due to the wide use of electronic products, digitally controlled DC-DC converters are attracting more and more attention in recent years. However, digital control strategies may introduce undesirable Limit Cycle Oscillation (LCO) due to quantization effects in the Analog-to-Digital Converter (ADC) and Digital Pulse Width Modulator (DPWM). This results in decreases in the quality of the output voltage and the efficiency of the system. Meanwhile, even if the resolution of the DPWM is finer than that of the ADC, LCO may still exist due to improper parameters of the digital compensator. In order to discover how LCO is generated, the state space averaging model is applied to derive equilibrium equations of a digital PID controlled DC-DC converter in this paper. Furthermore, the influences of the parameters of the digital PID compensator, and the resolutions of the ADC and DPWM on LCO are studied in detail. The amplitude together with the period of LCO as well as the corresponding PID parameters are obtained. Finally, MATLAB/Simulink simulations and FPGA verifications are carried out and no-LCO conditions are obtained.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 추계학술대회 논문집
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• pp.107-108
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• 2013

본 논문에서는 3-레벨 NPC(Neutral Point Clamped) 인버터에서 사용되는 SVPWM(Space Vector Pluse Width Modulation)기법들 중 옵셋전압을 이용한 대칭 SVPWM과 효율을 높이기 위한 전압 지령 벡터를 계산한 $120^{\circ}$ DPWM(Discontinuous PWM)과 $60^{\circ}(+30^{\circ})$ DPWM을 비교 분석하였다. 각 SVPWM간의 효율 및 THD를 비교 분석 하였고 이를 통해 시뮬레이션으로 스위칭 방식에 따라 비교하여 효율 및 THD 결과를 도출하였다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1325-1335
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• 2018

This paper presents a discontinuous pulse width modulation (DPWM) method to reduce switching losses in an indirect matrix converter (IMC) drive. The IMC has a number of power semiconductor switches. In other words, it consists of a rectifier stage and an inverter stage for AC/AC power conversion, which are composed of 12 and 6 switching devices, respectively. Therefore, the switching devices of the IMC suffer from high switching losses in the IMC drives. Various topologies to reduce switching losses have been studied by eliminating a number of switches from the rectifier stage. In this study, in contrast to prior research, a DPWM method is presented to reduce the switching losses of the inverter stage. The effectiveness of the proposed method to reduce switching losses in IMC drives is verified by simulations and experimental results.