• Proceedings of the KIPE Conference
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• 2000.07a
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• pp.347-350
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• 2000

This paper deals with the novel DPWM(discontinuous PWM) for 3-level inverter. Although DPWM methods generate higher harmonics than SVPWM they are of special interest because of their lower switching losses. And in the high modulation region the harmonic characteristics of DPWM is superior to the that of CPWM. However when DPWM applies to the 3-level inverter there is the problem that the output state is varied suddenly in the low modulation region($\textrm{m}_{I}$=0~0.5) The novel DPWM that this problem improves will be introduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.89-91
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• 2018

비엔나 정류기의 효율 개선을 위해 일반적으로 SVPWM이 가장 많이 사용되고 있다. 하지만 이보다 더 좋은 효율을 위해 스위칭 손실을 저감한 DPWM 기법에 대한 연구가 활발하게 진행되고 있는 상황이다. 본 논문에서는 DPWM 기법을 활용 시 발생되는 Power device의 손실을 분석하고, 커패시터 손실 및 수명을 추정 하는 연구를 진행했다.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.298-299
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• 2020

Triple Active Bridge 컨버터의 경부하 조건에서의 효율 개선을 위해 브리지의 듀티와 위상을 동시에 변경하는 Dual Pulse Width Modulation(DPWM)기법을 적용하였다. 기존의 위상천이기법은 제어가 단순한 장점이 있으나 경부하 조건에서 효율이 급격히 감소하는 단점이 존재한다. 따라서 본 논문에서는 DPWM 방식을 통해 경부하 조건의 효율 개선을 위한 각 브리지 듀티, 위상각을 분석하였고, 시뮬레이션을 통해 이를 검증하였다.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1207-1216
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• 2015

In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

• Journal of Power Electronics
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• v.3 no.4
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• pp.205-214
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• 2003

This paper proposes a simple control strategy based on the discontinuous PWM (DPWM) to balance the DC-link voltage of three-level neutral-point-clamped (NPC) inverter at low modulation index. It introduces new DPWM methods in multi-level inverter and one of them is used for balancing the DC-link voltage. The current flowing in the neutral point of the DC-link causes the fluctuation of the DC-link voltage of the NPC inverter. The proposed DPWM method changes the path and duration time of the neutral point current, which makes the overall fluctuation of the DC-link voltage zero during a sampling time of the reference voltage vector. Therefore, by using the proposed strategy, the voltage of the DC-link can be balanced fairly well and the voltage ripple of the DC-link is also reduced significantly. Moreover, comparing with conventional methods which have to perform the complicated calculation, the proposed strategy is very simple. The validity of the proposed DPWM method is verified by the experiment.

• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.138-139
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• 2014

3레벨 NPC 인버터는 구조상 DC Link가 두 개의 커패시터로 직렬 구성되어 있어 두 커패시터 간의 전압 불균형의 문제가 발생한다. 중성점의 변동으로 인하여 스위치 소자의 소손과 제어기의 오작동 등 시스템의 안정도가 떨어지게 된다. 기존의 중성점 전압을 제어하는 오프셋 전압 인가 방식은 zero point 지점에서 불연속 스위칭 구간이 존재하기 때문에 중성점 제어가 불가능하다. 본 논문에서는 중성점 전압을 제어하기 위하여 DPWM 기법에서 중성점 전압을 제어하는 방식을 제안하였다. DC Link의 두 커패시터 전압 불균형이 발생하면 $60^{\circ}(+30^{\circ})$ DPWM 기법으로 Positive 벡터와 Negative 벡터의 스위칭 인가 시간을 조절하여 두 커패시터의 전압 균형을 이루게 한다. 시뮬레이션을 통하여 본 논문에서 제안한 방식에 대한 타당성을 검증하였다.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.315-316
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• 2015

본 논문에서는 3-레벨 Neutral-Point-Clamped (NPC) 인버터의 DC-Link 중성점 전압 리플을 저감하여 인버터 출력 전압의 품질 신뢰성 향상이 가능한 새로운 Discontinuous Pulse Width Modulation (DPWM) 기법을 제안한다. NPC 인버터에서는 두 개의 커패시터로 이루어진 DC-Link 구조로 인해 상, 하단 DC-Link 커패시터 전압 불평형인 상황에서 DC-Link 중 성점 전압 리플이 발생한다. 중성점 전압 리플 발생 시 출력 전압의 품질을 보장할 수 없으며, 민감한 부하에 손상을 입힐 수 있다. 제안한 DPWM 알고리즘은 DC-Link 커패시터 전압을 조정하는 두 개의 오프셋을 사용하여 중성점 전압 리플을 저감한다. 또한, 시뮬레이션을 통해 본 논문에서 제안한 알고리즘의 타당성을 검증한다.

• Journal of IKEEE
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• v.21 no.2
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• pp.166-169
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• 2017

In this paper, maximum boost discrete PWM(DPWM) method of Z-Source Inverter(ZSI) is proposed. In general, a DPWM method is used to reduce the switching losses of the inverters and increase the efficiencies. The maximum boost PWM method of Z-Source Inverters is combined with the DPWM method. The proposed Maximum boost DPWM of ZSI is analyzed and it shows how to reduce the switching losses of ZSI. An experimental system has been built and tested to verify the effectiveness of the proposed method.

• Proceedings of the KIPE Conference
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• 2003.07b
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• pp.560-564
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• 2003

This paper proposes a simple control strategy based on the discontinuous PWM(DPWM) to balance the DC-link voltage of three-level Neutral-Point-Clamped(WPC) inverters at low modulation index. New DPWM methods in multi-level inverter are also introduced. The proposed DPWM method changes the path and duration to flow the neutral point current out of or into neutral point of the DC-link and it makes the overall fluctuation of the DC-link voltage zero during a sampling time of reference voltage vector. Therefore, the voltage of the DC-link can be balanced fairly well and also the voltage ripple of the DC-link is reduced significantly. Moreover, comparing with conventional methods, the proposed strategy is very simple. The validity of the proposed DPWM method is verified by experiment