• Journal of Smart Tourism
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• v.2 no.2
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• pp.15-19
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• 2022

Destination marketing organizations (DMOs) utilize the official website for marketing and promotional purposes, while tourists often navigate through the official website to gather necessary information for their upcoming trips. With the advancement of business analytics, DMOs may need to exploit the clickstream data generated through their official website to develop more suitable and persuasive strategic marketing and promotional activities. As such, the primary objective of the current study is to show whether clickstream data can successfully identify the trip purposes of a particular user. Using a latent class analysis and multinomial logistic regression, this study found the meaningful and statistically significant variations in webpage visits among different trip purpose groups (e.g., weekend getaways, day-trippers, and other purposes). The findings of this study would provide a foundation for more data-centric destination marketing and management practice.

• Proceedings of the Korean Vacuum Society Conference
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• 1997.02a
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• pp.146-146
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• 1997

• Journal of Broadcast Engineering
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• v.12 no.2
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• pp.177-184
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• 2007

In this paper, we compared two subjective assessment methods DSCQS(Double Stimulus Continuous Quality Scale method) and ACR(Absolute Category Rating). These methods are widely used in order to evaluate video quality for multimedia application. We performed subjective quality tests using DSCQS and ACR methods. The subjective scores obtained by the DSCQS and ACR methods show that these methods are highly correlated in terms of MOS(Mean Opinion Score) and have slightly lower correlation in terms of DMOS(Difference Mean Opinion Score). The results indicate that ACR method is an effective subjective quality assessment method, which shows compatible performance with DSCQS method and can evaluate a larger number of video sequences.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.152-159
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• 2004

In this study, we design the one-chip PWM IC with high voltage power switch (300V class LDMOSFET) for SMPS (Switching Mode Power Supply) application. Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain $({\simeq}65dB)$, unity frequency $({\simeq}190kHz)$ and large $PM(75^{\circ})$. comparator is designed with 2 stage. Saw tooth generators operate with 20kHz oscillation frequency. Also, we optimize drift concentration & drift length of n-LDMOSFET for design of high voltage switching device. It is shown that simulation results have the breakdown voltage of 350V. (using ISE-TCAD Simulation tool). PWM IC with power switching device is designed with 2um design rule and Bi-DMOS technology.

• The KIPS Transactions:PartB
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• v.16B no.2
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• pp.141-150
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• 2009

This paper proposes a system that can automatically write singing voices to music notes. First, the system uses Stabilized Diffusion Equation(SIDE) to divide the song to a series of syllabic parts based on pitch detection. By the song segmentation, our method can recognize the sound length of each fragment through clustering based on genetic algorithm. Moreover, this study introduces a concept called 'Relative Interval' so as to recognize interval based on pitch of singer. And it also adopted measure extraction algorithm using pause data to implement the higher precision of song transcription. By the experiments using 16 nursery songs, it is shown that the measure recognition rate is 91.5% and DMOS score reaches 3.82. These findings demonstrate effectiveness of system performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.105-112
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• 2009

In this paper, we investigated abnormal ESD failure on guard-rings in the smart power IC fabricated with $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology. Initially, ESD failure occurred below 200 V in the Machine Model (MM) test due to current crowding in the parasitic diode associated with the guard-rings which are generally adopted to prevent latch-up in high voltage devices. Optical Beam Induced Resistance Charge (OBIRCH) and Scanning Electronic Microscope (SEM) were used to find the failure spot and 3-D TCAD was used to verify cause of failure. According to the simulation results, excessive current flows at the comer of the guard-ring isolated by Local Oxidation of Silicon (LOCOS) in the ESD event. Eventually, the ESD failure occurs at that comer of the guard-ring. The modified comer design of the guard-ring is proposed to resolve such ESD failure. The test chips designed by the proposed modification passed MM test over 200 V. Analyzing the test chips statistically, ESD immunity was increased over 20 % in MM mode test. In order to avoid such ESD failure, the automatic method to check the weak point in the guard-ring is also proposed by modifying the Design Rule Check (DRC) used in BCD technology. This DRC was used to check other similar products and 24 errors were found. After correcting the errors, the measured ESD level fulfilled the general industry specification such as HBM 2000 V and MM 200V.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.25-34
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• 1995

A new vertical power MOSFET with over-current protection capability is proposed. The MOSFET consists of main power MOSFET cell, sensing MOSFET cell and lateral npn bipolar transistor. The proposed MOSFET may be fabricated by a conventional DMOS process without any additional fabrication step. Overcurrent state is sensed by the newly designed lateral bipolar transistor. Mixed-mode simulations proved that the overcurrent protection is achieved by the proposed MOSFET successfully with a small protection area less than 0.2 % of the total die area.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.164-165
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• 2007

파워 IC 공정은 CMOS 공정과 달리 내압별로 다양한 소자가 제공되며 BJT와 DMOS 구조를 포함할 경우 매스크가 20장이 넘는 매우 복잡한 공정이다. 본 논문에서는 국내의 파운드리 기업인 동부하이텍과 매그나칩사에서 제공하는 파워 IC 공정 및 제공되는 소자의 특성을 비교 분석하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2012.04a
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• pp.355-358
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• 2012

Although quality metrics for 2D video quality assessment have been proposed, the quality models on stereoscopic video have not been widely studied. In this paper, a new objective video quality metric for s tereoscopic video is proposed. The proposed algorithm consider three factors to evaluate stereoscopic video quality: blocking artifact, blurring artifact, and the difference between left and right view of stereoscopic vide o. The results show that the proposed algorithm has a higher correlation with DMOS than the others.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.1-6
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• 2009

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.