• Journal of the Korea Society of Computer and Information
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• v.11 no.5 s.43
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• pp.251-258
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• 2006

A Malicious code is used to SMiShing disguised as finance mobile Vishing, using Phishing, Pharming mail, VoIP service etc. to capture of personal information. A Malicious code deletes in Anti-Virus Spyware removal programs, or to cure use. By the way, the Malicious cord which is parasitic as use a DLL Injection technique, and operate are Isass.exe, winlogon.exe, csrss.exe of the window operating system. Be connected to the process that you shall be certainly performed of an exe back, and a treatment does not work. A user forces voluntarily a process, and rebooting occurs, or a blue screen occurs, and Compulsory end, operating system everyone does. Propose a treatment way like a bird curing a bad voice code to use a DLL Injection technique to occur in these fatal results. Click KILL DLL since insert voluntarily an end function to Thread for a new treatment, and Injection did again the Thread which finish an action of DLL, and an end function has as control Thread, and delete. The cornerstone that the treatment wav that experimented on at these papers and a plan to solve will become a researcher of the revolutionary dimension that faced of a computer virus, and strengthen economic financial company meeting Ubiquitous Security will become.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.829-832
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• 2005

This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.87-90
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• 2000

This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.

• Journal of IKEEE
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• v.27 no.3
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• pp.239-245
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• 2023

Whitelist-based ransomware solution is known as being vulnerable to false impersonation attack using DLL injection attack. To solve this problem, it is proposed to monitor DLL injection attack and to integrate the monitoring result to ransomware solutions. In this paper, we show that attackers can easily bypass the monitoring mechanism and then illegally access files of a target system. It means that whitelist-based ransomware solutions are still vulnerable.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10b
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• pp.660-660
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• 1998

본 논문은 SUN Solaris 2.6 환경에서 동작 중인 Dynamic Linking Library (DLL)를, 이 DLL을 사용하는 응용 프로그램의 동작에 영향을 주지 않고 온라인으로 교체하기 위한 방법을 제시한다. 구체적으로 이 논문은 Solaris 환경에서의 동적 링킹의 방법과 구조를 분석하고, 이로부터 DLL을 온라인으로 업그레이드하기 위한 교체 환경과 절차 및 방법을 제시하며, 실제 업그레이드를 통해 제시된 방법의 기능을 확인한다. 또한 제시된 방법을 동적 링킹을 사용하지 않은 일반 실행 파일의 온라인 교체에 활용하기 위한 방안을 제시한다.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.206-209
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• 2003

본 논문에서 제안하는 알고리즘은 심벌 타이밍 jitter 를 최소화하기 위해 가장 강한 신호를 주기적으로 감시하고, 그 신호를 적응적으로 DLL(Delayed Locked Loop)의 기준 신호로 정한다. 결과적으로 제안된 알고리즘은 DLL 추적 실패를 피할 수 있고, 기존의 알고리즘에 비하여 DLL의 정상 상태 추적 오류가 작다. 모의실험을 통하여 제안된 알고리즘의 정상상태 DLL 추적오류가 작고 다중 경로 상황에서 DLL 추적 실패를 피할 수 있음을 확인 하였다. 따라서 본 논문에서 제안하는 알고리즘은 OFDM 의 시간동기 복원 알고리즘에 적합하다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.79-85
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• 2004

A digitally-controlled analog-block inevitably undergoes the bang-bang oscillations which may cause a big amplitudes of the glitches if the oscillation occurs at the MSB transition points of a binary counter. The glitch results into the jitter noise for the case of the DLL. In this paper, we devise a new counter code that has the hysteresis in the bit transitions in order to prevent the transitions of the significant counter-bits at the locking state. The maximum clock jitter is simulated to considerably reduce over the voltage-temperature range guaranteed by specifications. The counter is employed to implement the high speed packet-base DRAM and contributes to the maximized valid data-window.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.33-39
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• 2013

There have been studies in improving jitter characteristic of delay locked loop (DLL) even it has a shorter jitter that of phase locked loop (PLL). These studies result in numerous architectures of DLL which improve jitter performance. The paper shows that the jitter characteristic can be improved with various loop filters in DLL. It has been designed with 1.8V $0.18{\mu}m$ CMOS process.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.607-608
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• 2008

Locking time of the DLL is the important design issue in case of clock gating for low power system. For precise analysis of the locking speed of the DLL, this paper analyzes the locking process of the DLL in time domain. Analysis result shows that the value of the DLL bandwidth over reference frequency should be limited to below 1 ($i.e.w_n/F_{REF}<1$) for the stable operation and relation between bandwidth and lock time is expressed by log function.