• Journal of information and communication convergence engineering
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• v.4 no.2
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• pp.75-78
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• 2006

This work presents a low complexity maximum-likelihood decoder for signal detection in VBLAST-STBC system, which employs non-square O-STBC code rate 3/4. Stacking received symbols from different symbol duration and applying QR decomposition result in the special format of upper triangular matrix R so that the proposed decoder is able to provide not only ML-like BER performance but also very low computational load. The low computational load and ML-like BER performance properties of the proposed decoder are verified by computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.4C
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• pp.303-309
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• 2006

By combining the space-time diversity technique and iterative turbo codes, space-time turbo codes(STTCS) are able to provide powerful error correction capability. However, the multi-path transmission and iterative decoding structure of STTCS make the decoder very complex. In this paper, we propose a low complexity decoder, which can be used to decode STTCS as well as general iterative codes such as turbo codes. The efficient implementation of the backward recursion and the log-likelihood ratio(LLR) update in the proposed algorithm improves the computational efficiency. In addition, if we approximate the calculation of the joint LLR by using the approximate ratio(AR) algorithm, the computational complexity can be reduced even further. A complexity analysis and computer simulations over the Rayleigh fading channel show that the proposed algorithm necessitates less than 40% of the additions required by the conventional Max-Log-MAP algorithm, while providing the same overall performance.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.11a
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• pp.209-210
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• 2011

In this paper, an area-efficient architecture of LDPC Decoder is proposed for DVB (Digital Video Broadcasting) 2.0 systems. The proposed LDPC Decoder was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of slices for the decoder is 56122 and the number of block RAM is 135.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.483-494
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• 1996

In this paper, we proposed the receive decoder and Virterbi algorithm with sliding multiple symbol detection using MLSE. the informationis transmitted by the phase difference of the adjacent channel signal at the .pi./4 shift QPSK. In order to apply the .pi./4 shift QPSK to TCM, we use the signal set expansion and the signal set partition by the phase differences. And the Viterbi decoder containing branch mertrice of the squared Euclidean distance of the first, second and Lth order phase difference is introduced in order to extract the information in the differential detection of the Trellis-Coded .pi./4 shift QPSK. The proposed Viterbi decoder and receiver are conceptually same to the sliding multiple symbol detection method using the MLSE. By uisng this method, the study shows that the Trellis-Coded .pi./4 shift QPSK is an attractive scheme for the power and the bandimited systems while also improving the BER performance when the Viterbi decoder is employed to the Lth order phase difference metrics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.249-254
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• 2005

This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.655-656
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• 2006

A parallel analog Viterbi decoder which decodes PR (1,2,2,1) signal of optical disc has been fabricated into chip. The proposed parallel analog Viterbi decoder implements the functions of the conventional digital Viterbi decoder utilizing the analog parallel processing circuits. In this paper, the analog parallel Viterbi decoding technology is applied for the PR signal. The benefit of analog processing is the low power consumption and the less silicon consumption. The test results of the fabricated chip are reported in this paper.

• Journal of the Semiconductor & Display Technology
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• v.13 no.4
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• pp.7-13
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• 2014

In this paper, an area-efficient degree-computationless modified Euclidean (DCME) algorithm is presented and implemented for high-speed Reed-Solomon (RS) decoder. The DCME algorithm can be used to solve the key equation in Reed-Solomon decoder to get the error location polynomial and the error value polynomial. A pipelined recursive structure is adopted for reducing the area of key equation solver (KES) block with sacrifice of an amount of decoding latency. For comparisons, KES block for RS(255,239,8) decoder with the proposed architecture is implemented using Verilog HDL and synthesized using Synopsys design tool and 65nm CMOS technology. The synthesis results show that the proposed architecture can be implemented with less gate counts than other existing DCME architectures.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.5
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• pp.575-582
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• 2014

One of the most important decision making is which product's components should make in-house and which should they outsource. This paper suggests a framework to solve above question. This paper applies to LCD TV industry with AHP analysis. The results shows that Scaler chip, LCD panel, MPEG decoder, and Video decoder are important components. Samsung Electronics turn out make in-house these core component. This research will be a good guideline for selecting core component.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.4 no.4
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• pp.278-285
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• 2011

This paper makes an analysis of the encoding structure and the decoding algorithm proposed by the DVB-S2 specification. The methods of implementing the LDPC decoder are fully serial decoder, the partially parallel decoder and the fully parallel decoder. The partial parallel scheme is the efficient selection to achieve appropriate trade-offs between hardware complexity and decoding speed. Therefore, this paper proposed an efficient memory structure for check node update block, bit node update block, and LLR memory.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.126-130
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• 2005

In this paper, a low-complexity maximum-likelihood (ML) decoder based on QR decomposition, called real-valued LCMLDec decoder or RVLCMLDec for short, is proposed for the Vertical Bell Labs Layered Space-Time (V-BLAST) architecture, a promising candidate for providing high data rates in future fixed wireless communication systems [1]. Computer simulations, in comparison with other detection techniques, show that the proposed decoder is capable of providingthe V-BLAST schemes with ML performance at low detection complexity.