Efficient LDPC Decoder for Digital Vedio Broadcasting Systems

디지털 방송 시스템을 위한 효율적인 LDPC 복호기 설계

  • Published : 2011.11.03

Abstract

In this paper, an area-efficient architecture of LDPC Decoder is proposed for DVB (Digital Video Broadcasting) 2.0 systems. The proposed LDPC Decoder was designed in hardware description language (HDL) and implemented with Xilinx Virtex-5 FPGA. With the proposed architecture, the number of slices for the decoder is 56122 and the number of block RAM is 135.

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