• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.266-266
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• 2009

This paper describes important parameters used to evaluate the insulation performance of power supply components in metro substations. For online fault diagnosis of power supply components, we have developed a new remote condition monitoring system using wireless technology. Our developed system can continuously monitor electric power equipment such as transformers, circuit brakers, and rectifiers and have powerful wireless networking functions.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.7 s.110
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• pp.659-664
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• 2006

This paper reports a high power 60 GHz push-push oscillator fabricated using $0.12{\mu}m$ metamorphic high electron-mobility transistors(mHEMTs). The devices with a $0.12{\mu}m$ gate-length exhibited good DC and RF characteristics such as a maximum drain current of 700 mA/mm, a peak gm of 660 mS/mm, an $f_T$ of 170 GHz, and an $f_{MAX}$ of more than 300 GHz. By combining two sub-oscillators having $6{\times}50{\mu}m$ periphery mHEMT, the push-push oscillator achieved a 6.3 dBm of output power at 59.5 GHz with more than - 35 dBc fundamental suppression. The phase noise of - 81.5 dBc/Hz at 1 MHz offset was measured. This is one of the highest output power obtained using mHEMT technology without buffer amplifier, and demonstrates the potential of mHEMT technology for cost effective millimeter-wave commercial applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.56-62
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• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• Journal of Hydrogen and New Energy
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• v.20 no.3
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• pp.202-207
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• 2009

A 75kW MCFC stack with the reactive area of 9,600cm$^2$ has been operated and validated in Boryeong thermal power plant. The 75kW MCFC stack was installed at the end of November 28, 2008 and started initial operation on December 23, 2008 after pretreated for about 20 days. At initial load operation, the stack showed the Open Circuit Voltage of 137V, which approaches the theoretical value. At the early stage of rated power operation, the stack displayed the voltage of 104V at the current of 754A and reached the maximum generating power of 78.5kW DC. This stack has been operated for 2,890 hours until April, 2009. In addition, the operation time of rated power records 1890 hours. This Operating result is scheduled to be reflected the design of l25kW stack.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.6 s.183
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• pp.166-173
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• 2006

In this study, a probe array has been developed for use in a data storage device that is based on scanning probe microscope (SPM) and MEMS technology. When recording data bits by poling the PZT thin layer and reading them by sensing its piezoresponse, commercial probes of which the tip heights are typically shorter than $3{\mu}m$ raise a problem due to the electrostatic forces occurring between the probe body and the bottom electrode of a medium. In order to reduce this undesirable effect, a poly-silicon probe with a high aspect-ratio tip was fabricated using a molding technique. Poly-silicon probes fabricated by the molding technique have several features. The tip can be protected during the subsequent fabrication processes and have a high aspect ratio. The tip radius can be as small as 15 nm because sharpening oxidation process is allowed. To drive the probe, electrostatic actuation mechanism was employed since the fabrication process and driving/sensing circuit is very simple. The natural frequency and DC sensitivity of a fabricated probe were measured to be 18.75 kHz and 16.7 nm/V, respectively. The step response characteristic was investigated as well. Overshoot behavior in the probe movement was hardly observed because of large squeeze film air damping forces. Therefore, the probe fabricated in this study is considered to be very useful in probe-based data storages since it can stably approach toward the medium and be more robust against external shock.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.8
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• pp.1227-1234
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• 2013

An analog array with a 1.2 double poly floating gate transistor has been developed with a standard CMOS fabrication process. The programming of each cell by means of an efficient control circuit eliminates the unnecessary erasing operation which has been widely used in conventional analog memories. It is seen that the path of the signal for both the programming and the reading is almost exactly the same since just one comparator supports both operations. It helps to eliminate the effects of the amplifier input-offset voltage problem on the output voltage for the read operation. In the array, there is no pass transistor isolating a cell of interest from the adjacent cells in the array. Instead of the extra transistors, one extra bias voltage, Vmid, is employed. The experimental results from the memory shows that the resolution of the memory is equivalent to the information content of at least six digital cells. Programming/erasing of each cell is achieved with no detectable disturbance of adjacent cells. Finally, the unique shape of the injector structure in a EEPROM is adopted as a cell of analog array. It reduces the programming voltage below the transistor breakdown voltage without any special fabrication process.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.6
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• pp.27-33
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• 1993

In order to improve complicated construction and complex control which are didvantage of optimal PWM technique aimed at harmonic elimination method, this paper presented MRA(Mode1 Reference Adaptive) PWM technique that gating signal of inverter is generated by comparing the reference signal with the induced feedback signal at the reference model of load. Design of controller is composed of microprocessor and analog circuit. MRA PWM technique used in the paper is able to compensate the degradation of voltage efficiency to be generated by the ratio of the output voltage to the DC supply voltage being low for using conventional sinusoidal PWM technique. When the trapezoidal signal is employed as the reference signal. the low order harmonics of line current can be reduced and the switching pattern is made by on-line computation using comparatively simple numerical analysis.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.7 no.2
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• pp.36-40
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• 1993

In order to improve complicated construction and complex control which are disadvantage of optimal PWM technique aimed at harmonic elimination method, this paper presented MRA(Model Reference Adaptive) PWM technique that gatmg signal of inverter is generated by comparing the reference signal with the induced feedback signal at the reference model of load. Design of controller is composed of microprocessor and analog circuit. MRA PWM technique used in the paper is able to compensate the degradation of voltage efficiency to be generated by the ratio of the output voltage to the DC supply voltage being low for using conventional sinusoidal PWM technique. When the trapezoidal signal is employed as the reference signal. the low order harmonics of line current can be reduced and the switching pattern is made by on-line computation using comparatively simple numerical analysis.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.319-319
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• 2013

Even though the fabrication methods of metal oxide based thin film capacitor have been well established such as RF sputtering, Sol-gel, metal organic chemical vapor deposition (MOCVD), ion beam assisted deposition (IBAD) and pulsed laser deposition (PLD), an applicable capacitor of printed circuit board (PCB) has not realized yet by these methods. Barium Strontium Titanate (BST) and other high-k ceramic oxides are important materials used in integrated passive devices, multi-chip modules (MCM), high-density interconnect, and chip-scale packaging. Thin film multi-layer technology is strongly demanded for having high capacitance (120 nF/$mm^2$). In this study, we suggest novel multi-layer thin film capacitor design and fabrication technology utilized by plasma assisted deposition and photolithography processes. Ba0.6Sr0.4TiO3 (BST) was used for the dielectric material since it has high dielectric constant and low dielectric loss. 5-layered BST and Pt thin films with multi-layer sandwich structures were formed on Pt/Ti/$SiO_2$/Si substrate by RF-magnetron sputtering and DC-sputtering. Pt electrodes and BST layers were patterned to reveal internal electrodes by photolithography. SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PE-CVD). The passivation layer plays an important role to prevent short connection between the electrodes. It was patterned to create holes for the connection between internal electrodes and external electrodes by reactive-ion etching (RIE). External contact pads were formed by Pt electrodes. The microstructure and dielectric characteristics of the capacitors were investigated by scanning electron microscopy (SEM) and impedance analyzer, respectively. In conclusion, the 0402 sized thin film multi-layer capacitors have been demonstrated, which have capacitance of 10 nF. They are expected to be used for decoupling purpose and have been fabricated with high yield.

• The Transactions of the Korean Institute of Power Electronics
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• v.18 no.2
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• pp.123-130
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• 2013

This paper proposes the switched trans Z-source inverter(STZSI) which combined the characteristics of the trans Z-source inverter(TZSI) and the switched inductor Z-source inverter(SLZSI). The proposed STZSI has the same performance compared with the SLZSI which is improved the voltage boost performance of the conventional typical X-shaped ZSI, and it has advantage that circuit structure of Z-impedance network is more simple. And, in order to step up the voltage boost factor under the condition of the same duty ratio, unlike the SLZSI adding the inductors and diodes, the proposed method is dune by changing the turn ratio of trans primary winding of Z-impedance network. To confirm the validity of the proposed method, PSIM simulation and a DSP(TMS320F28335) based experiment were performed using trans with turn ratio 1 and 2 under the condition of the input DC voltage VI=50V, duty ratio D=0.1 and D=0.15. As a result, under the same input/ouput condition, the inverter arm voltage stress of the proposed method is reduced to about 15%-22% as compared with typical X-shaped ZSI, and the elements in Z-impedance network of the proposed method is reduced as compared with the SLZSI.