• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.335-337
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• 1993

Offset voltage and drift characteristics of operational amplifier are critical factor to precision AID conversion System. In this study, a method is suggested to design the programmable A/D conversion system which has high resolution and low drift characteristics. First, hardware was designed to reduce the offset voltage of integrator and comparator, and analog switches are connected to reduce the drift characteristics of operational amplifier. And then, a calibration software technique was performed to obtain the stable data from A/D converter. The main advantage of our method is high precision A/D converter can be constructed with low cost and high confidence. Therefore proposed method is expected to be used in the industrial field where a high precision measurement is required.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.293-294
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• 2006

The conventional strain measuring device is costly and complicated - it is not simple to understand its structure. Hence, strain gage and the A/D converter are assembled to come up with a load and a strain measuring device. The device was tested for measuring the strain in a loaded specimen and the experimental results were compared to those obtained by a commercial strain indicator.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.571-572
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• 2008

We propose a 4-bit 1.6GSample/s flash-A/D converter realized in a digital 0.18um 1-poly 4-metal CMOS technology. To achieve low power with good performance, we employ immanent C2MOS comparator scheme. The kickback noise is one of the most important issue in A/D comparator performance. To decrease the effect of kickback noise, here we introduce kickback neutralization technique. The designed A/D converter has an effective number of bits(ENOBs) of 3.93 while using 32mW operating at 1.6GHz.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.153-156
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• 2001

This paper describes a 12-bit high speed pipeline CMOS A/D converter. The A/D converter simulated the 0.35${\mu}{\textrm}{m}$ n-well CMOS technology. The results show DNL and INL of $\pm$0.5LSB and $\pm$1.0LSB, conversion rate of 100Msamples/s, and power dissipation of 500㎽ with a power supply of 3.3V

• Journal of the Korean Institute of Telematics and Electronics
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• v.8 no.5
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• pp.1-9
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• 1971

An analog to digital converter Ivhich is applicable to mass production of digital multimeter is developed. The solid state digital instrument has accuracy $\pm$0.1% of feading $\pm$1 digit over 1 mV to 1000 volts with high input impedance and automatic function. All possibility to affect the distortion of A/D converter is tudied. As a result, useful linearity with high temperature stability of integrating waveforms is achieved by the very simplified circuit configuration to assure the proposed accuracy under various ambient condition.

• Journal of Power Electronics
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• v.17 no.1
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• pp.41-55
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• 2017

This study proposes a novel zero voltage transition (ZVT) pulse width modulation (PWM) DC-DC interleaved boost converter with an active snubber cell. All the semiconductor devices in the converter turn on and off with soft switching to reduce the switching power losses and improve the overall efficiency. Through the interleaved approach, the current stresses of the main devices and the ripple of the output voltage and input current are reduced. The main switches turn on with ZVT and turn off with zero voltage switching (ZVS). The auxiliary switch turns on with zero current switching (ZCS) and turns off with ZVS. In addition, the snubber cell does not create additional current or voltage stress on the main switches and main diodes. The proposed converter can smoothly achieve soft switching characteristics even under light load conditions. The theoretical analysis and operating stages of the proposed converter are made for the D > 50% and D < 50% modes. Finally, a prototype of the proposed converter is implemented, and the experimental results are given in detail for 500 W and 50 kHz. The overall efficiency of the proposed converter reached 95.5% at nominal output power.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1073-1081
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• 2005

This paper describes a 3.3 V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method. Most of Dfh converters with hiか speed current drive are an architecture choosing current switch cell, column, row decoding method but this decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. The designed D/A converter with an active chip area of $0.953\;mm^2$ is fabricated by using a 0.35um process. The simulation data shows that the rise/fall time, settling time, and INL/DNL are 1.92/2.1 ns, 12.71 ns, and a less than ${\pm}2.3/{\pm}58$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3 V is about 224 mW.

• Journal of Power Electronics
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• v.14 no.4
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• pp.641-648
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• 2014

This paper presents the design considerations and analysis for an interleaved boundary conduction mode power factor correction buck converter. A thorough analysis of the harmonic content of the AC line current is presented to examine the allowable voltage gain (K value) for meeting the EN61000-3-2, Class D standard while maximizing efficiency. The results of the harmonic analysis are used to derive the required value of K and therefore the output voltage necessary to meet the class D requirements for a given AC line voltage. The discussed design consideration and harmonic current analysis are verified on a 300W universal line experimental prototype converter with an 80V output. The measured efficiencies remain above 96% down to 20% of the full load. The input current harmonics also meet the IEC61000-3-2 (class D) standard.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.9
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• pp.1341-1350
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• 2017

In this paper, a high reliability 30W DC-DC converter is designed considering military standard (MIL-STD) for military applications such as guided weapon and aircraft. The performances and specifications of conventional military grade DC-DC converter are practically analyzed. The requirements for military grade DC-DC converter are established in consideration of MIL-STD and analysis results of conventional product. Two isolated DC-DC converter, forward and fly-back converter, are designed and compared to determine topology. From experimental results under various operating conditions, the forward topology satisfied performances and specifications of MIL-STD for military DC-DC converter.