• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.954-956
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• 2005

For transformer designers, eddy current loss calculation of steel structure is required to consider temperature rise on transformers. This study describes design of a lock plate for converter transformers by finite element method. The lock plate may be locally heated by fringing flux due to air-gap. 3D finite element analysis is performed and compared so as to minimize eddy loss on the lock plate with different materials and structures

• Journal of Industrial Technology
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• v.30 no.A
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• pp.69-73
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• 2010

In this paper, we designed the RF-DC converter used in wireless power transmission system and studied how to design the RF-DC converter of high conversion efficiency. The RF-DC converter operate at 2.45GHz and the diode is connected with series. The RF-DC converter uses shorted stub for DC loop and matching. We can divide the RF-DC converter circuit into four blocks. The reflection coefficients between the blocks were optimized for the maximum conversion efficiency at 0 dBm input power and $1300{\Omega}$ load impedance. The final design of the RF-DC converter has a 52 percent conversion efficiency.

• Transactions of the Korean Society of Automotive Engineers
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• v.17 no.1
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• pp.19-23
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• 2009

This paper focuses on vehicle fuel economy improvement using D-Range neutral control of automatic transmission. The system objected to reducing of fuel consumption during idle. Usually, turbine of conventional auto transmission is mechanically linked to wheel during idling condition. Therefore speed ratio of torque converter is zero for that period. This causes needless power loss by the torque converter slip. To improve this inefficiency automobile makers develops electronically-controlled D-range neutral control system. The D-range neutral control system minimizes slip on the torque converter by shifting gear to a neutral position during vehicle stoped with D-range gear position. However there's insufficient study about the effect of D-range neutral control system on vehicle fuel economy. In this paper, researches are performed on effect of D-range neutral control system on vehicle fuel economy by experiment with two different vehicle. And it is also estimated the effect on vehicle fuel economy using computer simulation. As a result, 1.8% of LA-4 mode fuel economy improvement can be achieved in a vehicle by D-range neutral control system.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.6
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• pp.67-76
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• 1997

In radar signal processing, an A/D converter with sufficient dynamic range and high sampling speed is required to detect the weakest target signals in heavy clutter and ECM environments. As the sampling frequency increases, the amount of digital data transfered to the signal processing module is also increased. To overcome these massive data transfer burden, we need an A/D conversion module with an enough data transfer rate. In this paper, we proposed an implementation scheme of a new A/D conversio module that can be used in multi-mode 3-D phased array radar signal processing system, and evaluated the performance. The proposed A/D conversion module is implemented with a standard A/D converter and a 6U-standard VME bus.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.3
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• pp.460-465
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• 2007

In this paper, the pipelined A/D converter with multi S/H stage structure is proposed for high resolution and high-speed data conversion rate. In order to improve a resolution and operational speed, the proposed structure increased the sampling time that is sampled input signal. In order to verify the operation characteristics 20MS/s pipelined A/D converter is designed with two S/H stage. The simulation result shows that INL and DNL are $0.52LSB{\sim}-0.63LSB$ and $0.53LSB{\sim}-0.56LSB$, respectively. Also, the designed Analog-to-Digital converter has the SNR of 43dB and power consumption is 18.5mW.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.481-482
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• 2007

This paper describes the design of a l0-bit 100 KSample/S CMOS A/D Converter for biomedical applications such as pulse oximetry, body weight scale, ECG etc. We adopted an asynchronous architecture in the 10-b DAC design and hence reduces the number of switches by 11 and resistors by 64 compared with the conventional l0-b DAC. We also reduced the power consumption compare with the conventional architecture by 0.4mW. Output offset cancellation technique is applied to the design of comparator. The total power consumption of designed circuit is 190uW at the supply voltage of 1.8V with the 0.18um general CMOS technology.

• Proceedings of the KIEE Conference
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• 1994.07a
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• pp.559-561
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• 1994

In this paper a new AC/DC/AC converter in which Soft-Switched-Inductor Module is used, is proposed. This new converter adopts ZVS(Zero-Voltage-Switching) for main switches. Therefore the switching loss is minimized and high frequency operation is possible. Operations principles, short analyses and computer simulation results are presented.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.137-140
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• 2002

This paper is proposed a 8-bit anolog to digital converter for CMOS image sensor. A anolog to digital converter for CMOS image sensor is required function to control gain. Proposed anolog to digital converter is used frequency divider to control gain. At 3.3 Volt power supply, total static power dissipation is 8mW and programmable gain control range is 30dB. The gain control range can be easily increased with insertion of additional flip-flop at divided-by-N frequency divider circuit.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.2
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• pp.459-467
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• 2017

An urban railway power substation consists of three thyristor dual converters. Two converters are connected to up and down trolley line to supply the electric energy or feed the regenerative energy back to the distribution. When the two converters break down, the remaining converter is used in an emergency. One thyristor dual converter system (TDCS) manages the energy of two or three railway stations. If the TDCS fails, the trains stop operating. To solve the problem, this paper proposes the three parallel operation control algorithm of thyristor dual converter system using the emergency converter. The broken TDCS can be replaced by the emergency converter in other TDCS. The effectiveness of this proposed control is verified by simulation.