• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 학술대회 논문집 전문대학교육위원
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• pp.161-165
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• 2002

The paper presents a diagnostic tool for analyzing the bit intermodulation in D/A converter. Bit intermodulation cause linearity errors which degrade the performance of the converter. A linear transformation of the Walsh transform of the integrated non-linearity diagram is shown to be sufficient to extract the bit intermodulation terms and their noise sensitivity. Practical applicability of the proposed method is shown by measurement.

• Journal of electromagnetic engineering and science
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• 제11권3호
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• pp.161-165
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• 2011

In this paper, a high-efficiency DC-AC converter is used for wireless energy transmission. The DC-AC convertter is implemented by combining the oscillator and power amplifier. Given that the conversion efficiency of a DC-AC converter is strongly affected by the efficiency of the power amplifier, a high-efficiency power amplifier is implemented using a class-E amplifier structure. Also, because of the low output power of the oscillator connected to the input stage of the power amplifier, a high-gain two-stage power amplifier using a drive amplifier is used to realize a high-output power DC-AC converter. The high-efficiency DC-AC converter is realized by connecting the oscillator to the input stage of the high-gain high-efficiency two-stage class-E power amplifier. The output power and the conversion efficiency of the DC-AC converter are 40.83 dBm and 87.32 %, respectively, at an operation frequency of 13.56 MHz.

• 전자공학회논문지B
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• 제31B권7호
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 학술회의 논문집 정보 및 제어부문 B
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• pp.361-364
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• 2003

In this paper, a high-resolution multibit sigma-delta modulator implemented in a.0.35-um CMOS technology is introduced. This modulator consists of two switched capacitor integrators, 3-bits A/D converter, and 3-bits D/A converter For the verification of the internal function blocks, HSPICE simulator is used. This circuit is normally operated at 130 MHz clock and the total power dissapation is 70 mW.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2001년도 High Temperature Superconductivity Vol.XI
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• pp.51-51
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• 2001

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.965_966
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• 2009

In this paper, a new soft-switching Two-switch Forward converter topology has been proposed. Compared with conventional two-switch forward converter, the proposed converter employs an auxiliary switch and a clamp capacitor to instead of two reset diodes, not only its duty cycle can exceed 0.5 to achieve wide range input voltage, but also soft switching can be achieved for all switches. Especially, voltage stress across main switches can be clamped at $1/2V_{in}$, voltage stress across auxiliary switch can be clamped at $V_{in}$. In addition, due to clamp capacitor series with the transformer, duty ratio can be extended with equation $V_o=\frac{V_{in}(1-D}D{N}$. Therefore, as a kind of better cost-effective approach, it is very attractive for high input, wide range and high efficiency application.

• 전자공학회논문지
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• 제54권2호
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• pp.47-52
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• 2017

본 논문에서는 생체 신호 처리를 위한 중간 속도를 갖는 A/D 변환기 설계를 위하여 1.8V 전원의 CMOS SAR(Successive Approximation Register) A/D 변환기를 설계하였다. 본 논문에서 C-DAC Array의 MSB단을 4분할하여 선형성을 향상시킨 10비트 SAR A/D 변환기 설계를 제안한다. 아날로그 입력이 인가되는 MSB 단의 전하가 충전되는 시간을 확보하여 선형성을 높였다. MSB단이 아날로그 입력을 샘플링하는 블록이기 때문에 초기 값을 보다 정교하게 받아들이는 원리를 통해 선형성을 확보하였다. C-DAC에서 Split 커패시터를 사용하여 면적을 최소화하고, 전력을 감소시켰다. 제안된 SAR A/D 변환기는 0.18um CMOS 공정을 이용하여 설계하였고, 공급 전압 1.8V에서 4MS/s의 변환속도를 가지며, 7.5비트의 ENOB(Effective Number of Bit)이 측정되었다. $850{\times}650um^2$의 면적, 총 전력소모는 123.105uW이고, 170.016fJ/step의 FOM(Figure of Merit)을 확인할 수 있다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.40-41
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• 2016

The inverter resistance welder requires AC/DC converter of high efficiency because the converter changes a commercial ac power source to low voltage dc power source. Harmonic components that occur in the conversion process of converter decrease system power factor and deal great damage in electric power system. To improve such problems, this paper proposes a high efficiency AC/DC converter for inverter resistance welder. The switching devices in the proposed converter are operated by soft switching technique using a new quasi-resonant circuit. As a result, the proposed AC/DC converter obtains low switching power loss and high efficiency.

• 한국광학회지
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• 제14권4호
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• pp.454-459
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• 2003

단일 모드 광원이 집적된 Mach-Zehnder간섭계형 파장 변환기를 제작하여 세계 최초로 10 Gb/s에서 파장 변환 특성을 확인하였다. 제작된 파장 변환기는 수동 도파로 영역에서의 전파 손실을 줄이기 위해 undoped InP층이 수동 도파로 위에 형성된 새로운 BRS 구조를 사용하였다. 단일 모드 광원으로 손실 결합형 분포 궤환형 반도체 레이저(loss-coupled distributed feedback laser; LC-DFB LD)를 사용하여, 파장 변환기에 있는 반도체 광증폭기의 주입전류가 200 mA까지 측모드 억제율이 30 dB 이상의 값을 나타내었다. 제작된 LC-DFB LD 집적 파장 변환기는 10 Gb/s의 동적 파장 변환 특성 측정 결과, 7 dB 정도의 소광비를 갖는 eye 패턴을 얻을 수 있었으며, power penalty는 $10^{-9}$ bit error rate에서 2.8 dB의 값을 나타내었다.

• 전기학회논문지
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• 제63권9호
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• pp.1212-1218
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• 2014

For OBC (On-Board Charger) and LDC (Low DC-DC Converter) used as essential power conversion systems of PHEV (Plug-in Hybrid Electric Vehicle), system performance is required as well as reliability, which is need to protect the vehicle and driver from various faults. While current development processor is sufficient for embodying functions and verifying performance in normal state during development of prototypes for OBC and LDC, there is no clear method of verification for various fault situations that occur in abnormal state and for securing stability of vehicle base, unless verification is performed by mounting on an actual vehicle. In this paper, a CCM (Charger Converter Module) was developed as an integrated structure of OBC and LDC. In addition, diverse fault situations that can occur in vehicles are simulated by a simulator to artificially inject into power conversion system and to test whether it operates properly. Also, HILS (Hardware-in-the-Loop Simulation) is carried out to verify whether LDC is operated properly under power environment of an actual vehicle.