• Journal of Power Electronics
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• 제2권2호
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• pp.112-123
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• 2002

This paper presents a novel prototype of the utility AC power interfaced soft-switching sinewave pulse modulated inverter using the high-frequency flyback for the small scale distributed renewable energy power conditioner. The proposed cricuit with a high-frequency isolation link has a funtion of electrical isolation, which is more cost-effective and reliable for the small-scale distributed renwal energy utilization system from a safety point of riew. The discontinuous conduction mode(DCM) operation of the high-frequency flyback transformer is adopted to establish a simple and low-cost circuit configuration and control scheme. For the simplicity, the circuit operating principle is described on the basis of the modified conventional full bridge inverter, whitch is the typical conventional high-frequency full-bridge inverter employing the high requency flyback transformer to eanble the effictive function of the electrical isolation. Than, the new circuit topology of the unility-interfaced soft-switching sinewave pulse modulated inverter using IGBTs is proposed. The proposed cricuit topology is additionally composed of the auxiliary power regenerating snubber cricuits, which are also mathematically analyzed for the parameter desigen settings. Finally, the performance of the propose inverter is evaluated on the basis of computer-aid simulation. It is noted that the sinewave pulse modulated output current of the inverter is synchronous to the AC main voltage.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 A
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• pp.254-257
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• 1993

This paper presents a new method to implement Hebbian learning method on artificial neural network. In hebbian learning algorithm, complexity in terms of multiplications is high. To save the chip area, we consider a new learning circuit. By calculating similarity, or correlation between $X_i$ and $O_i$, large portion of circuits commonly used in conventional neural networks is not necessary for this new hebbian learning circuit named COR. The output signals of COR is applied to weight storage capacitors for direct control the voltages of the capacitors. The weighted sum, ${\Sigma}W_{ij}O_j$, is realized by multipliers, whose output currents are summed up in one line which goes to learning circuit or output circuit. The drain current of the multiplier can produce positive or negative synaptic weights. The pass transistor selects eight learning mode or recall mode. The layout of an learnable six-neuron fully connected Hopfield neural network is designed, and is simulated using PSPICE. The network memorizes, and retrieves the patterns correctly under the existence of minor noises.

• 조명전기설비학회논문지
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• 제24권4호
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• pp.1-9
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• 2010

LED구동회로및 제어회로를 개발하였다. 개발된 LED구동회로는 새로운 PWM회로를 가지고 있으며 LED열의 디밍, 전류 및 온도제어 및 통신 기능을 할 수 있다. 개발된 PWM회로는 기본적인 디지털 논리소자를 사용하여 만들어 질 수 있는 두 개의 링 발진기와 한 개의 카운터로 구성되어 있다. 부가적으로 이 회로는 온-오프 제어 모드, 비상모드, 전력절감모드를 가지고 있으며 직열통신을 이용해서 제어된다. 설계 된 PWM 발생기와 제어회로는 마그나칩/하이닉스의 디지털 공정을 이용하여 제작되었다. 제작된 칩은 LED구동장치와 제어기 보드에 장착되어 테스트 되었으며 성공적으로 동작하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권4호
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• 한국정보전자통신기술학회논문지
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• 제12권3호
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• pp.312-320
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• 2019

본 논문에서는 110nm eFlash 셀을 사용한 512Kb eFlash IP를 설계하였다. eFlash 셀의 프로그램, 지우기와 읽기 동작을 만족시키는 row 구동회로(CG/SL 구동회로), write BL 구동회로( write BL 스위치 회로와 PBL 스위치 선택 회로), read BL 스위치 회로와 read BL S/A 회로와 같은 eFlash 코어회로(Core circuit)를 제안하였다. 그리고 프로그램 모드에서 9.5V와 erase 모드에서 11.5V의 VPP(Boosted Voltage) 전압을 공급하는 VPP 전압 발생기회로는 기존의 단위 전하펌프 회로로 cross-coupled NMOS 트랜지스터를 사용하는 대신 body 전압을 ground에 연결된 12V NMOS 소자인 NMOS 프리차징 트랜지스터의 게이트 노드 전압을 부스팅하는 회로를 새롭게 제안하여 VPP 단위 전하펌프의 프리차징 노드를 정상적으로 VIN(Input Voltage) 전압으로 프리차징 시켜서 VPP 전하펌프 회로의 펌핑 전류를 증가시켰다. 펌핑 커패시터로는 PMOS 펌핑 커패시터에 비해 펌핑전류가 크고 레이아웃 면적이 작은 12V native NMOS 펌핑 커패시터를 사용하였다. 한편 110nm eFlash 공정을 기반으로 설계된 512Kb eFlash 메모리 IP의 레이아웃 면적은 $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$이다.

• 전기학회논문지P
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• 제63권4호
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• pp.248-253
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• 2014

Generally, power factor correction (PFC) techniques play an important role in the power supply technology. Many new circuit topologies and control strategies for PFC have been proposed. Among them, the brideless PFC (BPFC) reduces the number of switching devices and the losses and improves the power density as well. Moreover, by implementing the improved topology in the discontinous conduction mode (DCM) it ensures almost unity power factor in a simple and effective manner. In the DCM operation gives additional advantages such as zero-current turn-on in the power switches, zero-current turn-off in the output diode and reduces the complexity of the control circuitry. In this paper, a new control strategy for the BPFC is proposed. Also, the performance of the proposed system is demonstrated through experiments.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.919-922
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• 2003

This paper presents a novel low power driving circuit for passive matrix organic lighting emitting diodes (OLED) displays. The proposed driving method for a low power OLED driving circuit which reduce large parasitic capacitance in OLED panel only use current driving method, instead of mixed mode driving method which uses voltage pre-charge technique. The driving circuit is implemented to one chip using 0.35${\mu}{\textrm}{m}$ CMOS process with 18V high voltage devices and it is applicable to 96(R.G.B)X64, 65K color OLED displays for mobile phone application. The maximum switching power dissipation of driving power dissipation is 5.7mW and it is 4% of that of the conventional driving circuit.

• 전기전자학회논문지
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• 제22권3호
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• pp.548-557
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• 2018

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 추계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.271-273
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• 2002

Switching power supply are widely used in many industrial field. Power factor correction(PFC) has become an increasingly necessary feature in new power supply designs. The power factor correction circuit using boost converter used in input of power source is studied in this paper. In a boost power factor correction circuit there are two feedback control loops, which are a current feedback loop and a voltage feedback loop. In this paper, it is analyzed regulation performance of output voltage and compensator to improve of transient response that presented at continuous conduction mode(CCM) of boost PFC circuit. The validity of designed boost PFC circuit is confirmed by simulation and experimental results.

• 대한전기학회논문지:시스템및제어부문D
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• 제50권11호
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• pp.550-556
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• 2001

The computerized cardiac analysis system, which acquires and analyzes the electrical activation signal propagating along the surface of the heart, is indispensible equipment for the open heart surgery and electrical cardiac study. In this paper, the design requirement and the electrical circuit analysis are performed to construct the multi-channel cardiac activation pre-amplifier necessary for a signal conditioning circuit. The general 64 channel configuration is expanded into 128 channels to enhance the spatial resolution on the mapped surface of the heart. The 128 channels pre-amplifier consists of input circuit, differential amplifier, right leg driven circuit and isolation part. It has distinct features; high voltage protection, leakage current limitation, isolation and the maximization of common mode rejection ratio with respect to the half-cell potential difference due to different electrode materials. The final pre-amplifier circuit is assembled with 8 boards, each of which composing of 16 channels.