• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• Journal of Power Electronics
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• 제9권6호
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• pp.903-910
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• 2009

In this paper, a digital average current mode control using diode current sensing technique is proposed. Although the conventional inductor current sensing technique is widely used, the sensed signal of the current is negative. As a result, it requires an additional circuit to be applied to general digital controller ICs. The proposed diode current sensing method not only minimizes the peripheral circuit around the digital IC but also consumes less power to sense current information than the inductor current sensing method. The feasibility of the proposed technique is verified by experiments using a 500W power factor correction (PFC) boost rectifier.

• 한국전자통신학회논문지
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• 제15권3호
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• pp.487-494
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• 2020

본 논문에서는 정적소비전력을 줄이며, 전류 모드 신호처리의 장점을 최대로 올릴 수 있는 전류 메모리 회로 설계를 제안한다. 제안하는 전류 메모리 회로는 기존의 전류 메모리 회로가 갖는 Clock-Feedthrough와 Charge-Injection 등으로 인해 데이터 저장 시간이 길어지면서 전류 전달 오차가 심해지는 문제를 최소화하며, 저전력 동작이 가능한 Current Transfer 구조에 밀러 효과(Miller effect)를 극대화하는 Support MOS Capacitor를 삽입하는 설계로, 저장 시간에 따르는 개선된 전류 전달 오차를 보였다. 매그나칩/SK하이닉스 0.35㎛ 공정으로 칩 제작을 통한 실험 결과, 저장 시간에 따르는 전류 전달 오차가 5% 이하로 개선되는 것을 검증하였다.

• 전기학회논문지P
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• 제57권3호
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• pp.260-264
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• 2008

In this paper, a dual mode baseband analog channel selection filter is described which is designed for the Bluetooth and WCDMA wireless communications. Using the presented current-mode integrator, a dual mode channel selection filter is designed. To verify the current-mode integrator circuit, Hspice simulation using 1.8V Hynix $0.18{\mu}m$ standard CMOS technology was performed and achieved $50.0{\sim}4.3dB$ gain, $2.29{\sim}10.3MHz$ unity gain frequency. The described third-order dual mode analog channel selection filter is composed of the current-mode integrator, and used SFG(Signal Flow Graph) method. The simulated results show 0.51, 2.40MHz cutoff frequency which is suitable for the Bluetooth and WCDMA baseband block each.

• 전자공학회논문지 IE
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• 제47권2호
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• pp.13-20
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• 2010

본 논문에서는 PWM을 활용한 전류모드 고효율 PWM DC-DC 전원변환 집적회로(Integrated Circuit)를 설계하였다. IC에 인가할 수 있는 최대 전압은 40[V]이며 입력 전압이 DC 2.8[V]~330[V]일 때 출력 전압을 이 보다 높은 전압으로 바꿀 수 있는 한편 외부 저항비나 트랜스의 권선비를 조정하여 원하는 DC 전압을 만들어 낼 수 있다. 출력전압의 3[%] 오차를 유지하면서 3[A] 이상의 전류를 부하에 공급할 수 있도록 구현하였다. 제작공정은 0.6[um], 2P_2M CMOS 공정을 사용하였다. 전원전압이 3.6[V]일 때 대기상태에서 소비전력은 1[mW]이하이고 최대 전력변환 효율은 약 86[%]이다. 칩 사이즈는 2100*2000[um2]이며, 칩을 소형패키지에 내장하여 조립하였기 때문에 휴대형기기나 소형 전자기기에 적용이 편리하게 되어 있다.

• 대한전자공학회논문지SD
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• 제41권4호
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• pp.67-74
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• 2004

기존의 버스트 모드 자동전력제어 회로는 데이터 율이 증가함에 따라 마크밀도 변화 영향을 심하게 받아 에러를 야기하였다. 이 문제를 해결하기 위해 높은 데이터 율에서도 마크밀도의 영향을 배제시킬 수 있는 새로운 구조의 첨두 비교기를 고안하고 이를 자동전력제어 회로에 적용하여 마크밀도 변화에 강한 버스트 모드 자동전력제어 회로를 제안하였다. 제안한 자동전력제어 회로 내의 첨두 비교기는 높은 데이터 율에서 뿐만 아니라 광범위한 기준전류 및 차 전류 변화에서도 미소한 마크밀도 변화 영향만을 보여 마크밀도 변화에 매우 강한 특성을 확인 할 수 있었다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제48권9호
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• pp.467-475
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• 1999

This paper presents an analysis method of a forward converter, using both the finite element method considering the external circuit and a state variables equation. The converter operates at 50kHz and its one period is divided into two modes for the simplicity of the analysis. In the first mode, the switching transistor turns on and an input power is transferred into the load by the electromagnetic conversion action of a ferrite transformer. In the second mode, the switching transistor turns off and the stored energy in an inductor is delivered to the load, and the transformer core is demagnetized by the reset winding current. In this paper, time-stepping finite element method taking into account the on-state electrical circuit of the converter in used to analyze both the electrical circuit and electromagnetic field of the magnetic device during the first mode and the demagnetization period of the transformer core. Then a state variables equation for the circuit which the inductor current flows is constituted and solved during the second mode. As a result, the simulation results have been good agreement with the results obtained form experiment.

• 전기학회논문지
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• 제60권4호
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• pp.871-876
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• 2011

In this paper, a voltage-controlled frequency tunable current-mode integrator and a 3rd-order current-mode Chebyshev filter in 1.8V-$0.18{\mu}m$ CMOS is realized for software radio applications in system-on-chips. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power consumption of the designed filter can be reduced by using a current-mode small size integrator. And also, cutoff frequency of this filter is variable between 1.2MHz and 10.1MHz, the power consumption is 2.85mW. And the voltage bias compensated circuit is used to control the voltage variation.in the designed filter.

• Journal of Welding and Joining
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• 제15권2호
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• pp.72-80
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• 1997

The spatter generation rate of GMA welding with $CO_2$ gas shielding was measured with the change of welding conditions such as wire feeding rate and welding voltage and then the results were analized with the accompanying changes in metal transfer mode and in bead geometry. The spatter generation rate (SGR) was relatively low not only wit the short circuit transfer but with the truely globular transfer mode. However, the SGR resulted with the mixed mode were consistantly high. The resultant wave pattern of mixed mode was due to the coexistance of short-circuit and globular transfer and characterized by the frequent appearance of instantaneous short circuit. Considering the result of SGR and that of bead geometry, it could be concluded that when the wire feeding rate (or welding current) was either low or high, the optimum bead shape could be obtained along with the low spatter generation. However, in the middle range of wire feeding rate, the optimum bead shape was only obtained in the mixed mode condition resulting in the high spatter generation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.514-517
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• 1998

This paper proposed a symmetric feedback current enhancement circuit with 1.5V power supply to design a 3$^{rd}$ order butterworth low pass filter. The proposed filter designed on 0.8.mu.m CMOS n-well double poly/double metal process simulated in HSPICE composed of the 3dB frequency enhancement circuit and the unity-gain frequency enhancement circuit. The simulation result on the design filter shows the badnwith of 25MHz, phase of 92.6 .deg. and power consumption of 0.3mW..