• Proceedings of the KIEE Conference
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• summer
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• pp.1214-1216
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• 2004

Conventional Switched Mode Power Supplies(SMPS) with diode-capacitor rectifier have distorted input current waveform with high harmonic contents. Typically, these SMPS have a power factor lower than 0,65. To improve with this problem the power factor correction(PFC) circuit of power supplies has to be introduced. PFC circuit have tendency to be applied in new power supply designs. The input active power factor correction circuits can be implemented using either the two-stage or the single-stage approach. In this paper, the comparative analysis of power factor correction circuit using feedforward control with average current mode single-stage flyback method converter and two-stage converter which is combination of boost and flyback converter. The two prototypes of 50W were designed and tested a laboratory experimental. Also, the comparative analysis is confirmed by simulation and experimental results.

• Proceedings of the KIEE Conference
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• 2004.04a
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• pp.136-139
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• 2004

This paper presents a buck circuit topology of high-frequency with a single switching element. It solved the problem which arised from hard-switching in high-frequency using a resonant snubber and operating under the principle of ZCS turn-on and ZVS turn-off commutation schemes. In the existing circuit, it has the voltage stress which is twice of input voltage in free-wheeling diode. But in the proposed circuit, it has voltage stress which is lower than input voltage with modifing a location of free-wheeling diode. In this paper, it explained the circuit operation of each mode and confirmed the waveform of each mode with simulation result. Also the experiment result verified the simulation waveform and compared the existing voltage stress of free-wheeling diode with the proposed voltage stress of that. Moreover, it compares and analyzes the proposed circuit's efficiency with the hard-switching circuit's efficiency according to the change of load current.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2008.04a
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• pp.247-250
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• 2008

최근 무선통신용 LSI는 배터리 수명과 관련하여, 저전력 동작이 중요시되고 있다. 따라서 Digital CMOS 신호처리와 더불어 동작 가능한 SI (Switched-Current) circuit를 이용하는 Current-mode 신호처리가 주목받고 있다. 그러나 SI circuit의 기본인 Current Memory는 Charge Injection에 의한 Clock Feedthrough라는 문제점을 갖고 있기 때문에, 전류 전달에 있어서 오차를 발생시킨다. 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 해결방안으로 CMOS Switch의 연결을 검토하였고, 0.25${\mu}m$ CMOS process에서 Memory MOS와 CMOS Switch의 Width의 관계는 simulation 결과를 통하여 확인하였으며, MOS transistor의 관계를 분명히 하여, 설게의 지침을 제공한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.35-40
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• 2012

In DC-DC converters, a PWM/PFM dual mode control method is commonly used to maintain a high efficiency over a wide range of load variation. Since the control mode is selected according to the load condition, the chip area is increased due to additional circuit for mode control and the optimum efficiency cannot be achieved around the mode transition point. To solve such problems, a new integrated control method is proposed in this paper, in which a PLL is used in the current mode PWM control circuit instead of an oscillator. The proposed integrated control method is verified through a design of a buck converter using PSIM simulation. Simulation of the complete buck converter circuit by Cadence Spectre showed a maximum efficiency of 94.7% at a load current of 250mA and an efficiency of 85.4% at a load current of 10mA under the light load condition.

• Journal of IKEEE
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• v.15 no.4
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• pp.319-323
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• 2011

In this paper presents a new model of dual-mode synchronous buck converter with dynamic control for mobile applications was proposed. The proposed circuit can operate at 2.5MHz with supply voltage 2.5V to 5V for low ripple and minimum inductor and capacitor size, which is suitable for single-cell lithium-ion battery supply mobile applications. For high efficiency, the proposed circuit adopts synchronous type and dynamic control. The proposed circuit is designed by using the device parameter of TSMC 0.18um BCD process and the performance is evaluated by Cadence spectre. Experimental board level results show the maximum conversion efficiency is 96% at 100mA load current.

• Journal of Power Electronics
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• v.15 no.5
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• pp.1329-1337
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• 2015

By placing distributed generation power sources beside a big nonlinear load, these sources can be used as a power quality enhancer, while injecting some active power to the network. In this paper, a new scheme to use the distributed generation power source in both operation modes is presented. In this scheme, a fuzzy controller is added to adjust the optimal set point of inverter between compensating mode and maximum active power injection mode, which works based on the harmonic content of the nonlinear load. As the high order current harmonics can be easily rejected using passive filters, the DG is used to compensate the low order harmonics of the load current. Multilevel transformerless cascade inverters are preferred in such utilization, as they have more flexibility in current/voltage waveform. The proposed scheme is simulated in MATLAB/SIMULINK to evaluate the circuit performance. Then, a 1kw single phase prototype of the circuit is used for experimental evaluation of the paper. Both simulative and experimental results prove that such a circuit can inject a well-controlled current with desired harmonics and THD, while having a smaller switching frequency and better efficiency, related to previous 3-phase inverter schemes in the literature.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.2
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• pp.133-138
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• 2014

This paper proposes a low power-loss averaging current mode control using a resistor and bypass switch. Generally, current sensing method using a resistor has a disadvantage of power loss which degrades the efficiency of the entire systems. On the other hand, proposed measurement technique operating with bypass-switch connected in parallel with sensing resistor can reduce power loss significantly the current sensor. An analog-circuited bypass driver is implemented and used along with an average-circuit mode controller. The bypass switch bypasses the sensing current with a small amount of power loss. In this paper, a 50[W] prototype average current mode boost converter has been implemented for the experimental verification.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.240-249
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• 2018

Individual DC voltage balance problem is an inherent issue for cascaded H-bridge (CHB) based converter. When the CHB-based static synchronous compensator (STATCOM) is operating at zero current mode, the software-based individual DC voltage balancing control techniques may not work because of the infinitesimal output current. However, the different power losses of each cell would lead to the individual DC voltages unbalance. The uneven power losses on the local supplied cell-controllers (including the control circuit and drive circuit) would especially cause the divergence of individual DC voltages, due to their characteristic as constant power loads. To solve this problem, this paper proposes an adaptive voltage balancing module which is designed in the cell-controller board with small size and low cost circuits. It is controlled to make the power loss of the cell a constant resistance load, thus the DC voltages are balanced in zero current mode. Field test in a 10kV STATCOM confirms the performance of the proposed method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07b
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• pp.1254-1257
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• 2004

This paper presents a built-in current sensor(BICS) that can detect defects in CMOS integrated circuits through current testing technique - Iddq test. Current test has recently been known to a complementary testing method because traditional voltage test cannot cover all kinds of bridging defects. So BICS is widely used for current testing. but there are some critical issues - a performance degradation, low speed test, area overhead, etc. The proposed BICS has a two operating mode- normal mode and test mode. Those methods minimize the performance degradation in normal mode. We also used a current-mode differential amplifier that has a input as a current, so we can realize higher speed current testing. Furthermore, only using 10 MOSFETS and 3 inverters, area overhead can be reduced by 6.9%. The circuit is verified by HSPICE simulation with 0.25 urn CMOS process parameter.