• 센서학회지
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• 제28권5호
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• pp.284-288
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• 2019

A calibration-free analog neuron circuit is proposed as a viable alternative to the power hungry digital neuron in implementing a deep neural network. The conventional analog neuron requires calibrations because a voltage-mode link is used between the soma and the synapse, which results in significant uncertainty in terms of current mapping. In this work, a current-mode link is used to establish a robust link between the soma and the synapse against the variations in the process and interconnection impedances. The increased hardware owing to the adoption of the current-mode link is estimated to be manageable because the number of neurons in each layer of the neural network is typically bounded. To demonstrate the utility of the proposed analog neuron, a simple neural network with $4{\times}7{\times}3$ architecture has been designed for classifying iris flowers. The chip is now under fabrication in 0.35 mm CMOS technology. Thus, the proposed true current-mode analog neuron can be a practical option in realizing power-efficient neural networks for edge computing.

• 한국지능시스템학회:학술대회논문집
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• 한국지능시스템학회 2008년도 춘계학술대회 학술발표회 논문집
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• pp.247-250
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• 2008

최근 무선통신용 LSI는 배터리 수명과 관련하여, 저전력 동작이 중요시되고 있다. 따라서 Digital CMOS 신호처리와 더불어 동작 가능한 SI (Switched-Current) circuit를 이용하는 Current-mode 신호처리가 주목받고 있다. 그러나 SI circuit의 기본인 Current Memory는 Charge Injection에 의한 Clock Feedthrough라는 문제점을 갖고 있기 때문에, 전류 전달에 있어서 오차를 발생시킨다. 본 논문에서는 Current Memory의 문제점인 Clock Feedthrough의 해결방안으로 CMOS Switch의 연결을 검토하였고, 0.25${\mu}m$ CMOS process에서 Memory MOS와 CMOS Switch의 Width의 관계는 simulation 결과를 통하여 확인하였으며, MOS transistor의 관계를 분명히 하여, 설게의 지침을 제공한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.518-521
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• 1998

This paper describes a 3.3V-65MHz 12BIT CMOS current-mode DAC designed with a 8 MSB current matirx stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch ahs been employed. The simulation results of the designed DAC show a coversion rate of 65MHz, a powr dissipation of 71.7mW, a DNL of .+-.0.2LSB and an INL of .+-.0.8LSB with a single powr supply of 3.3V for a CMOS 0.6.mu.m n-well technology.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.689-692
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• 1999

This paper describes a 10-bit 75-MHz CMOS current-mode DAC designed for 0.8${\mu}{\textrm}{m}$ double-poly double-metal CMOS technology. This D/A converter is implemented using a current cell matrix that can drive a resistive load without output buffer. In the DAC. a current source is proposed to reduce the linearity error caused by the threshold-voltage variations over a wafer and the glitch energy caused by the time lagging, The integral and differential linearity error are founded to be within $\pm$0.35 LSB and $\pm$0.31 LSB respectively. The maximum conversion rate is about 80 MS/s. The total power dissipation is 160 ㎽ at 75 MS/s conversion rate.

• Journal of Information Display
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• 제3권3호
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• pp.35-43
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• 2002

Silicon-based 0.69-inch AMOEL microdisplay with integrated driver and timing controller circuits for microdisplay applications has been developed using 0.35 ${\mu}m$ l-poly 4-metal standard CMOS process with 5 V CMOS devices and CMP (Chemical Mechanical Polishing) technology. To reduce the large data programming time consumed in a conventional current programming pixel circuit technique and to achieve uniform display, de-amplifying current mirror pixel circuit and the current-mode data driver circuit with threshold roltage compensation are proposed. The proposed current-mode data driver circuit is inherently immune to the ground-bouncing effect. The Monte-Carlo simulation results show that the proposed current-mode data driver circuit has channel-to-channel non-uniformity of less than ${\pm}$0.6 LSB under ${\pm}$70 mV threshold voltage variaions for both NMOS and PMOS transistors, which gives very good display uniformity.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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• pp.278-281
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• 1988

This paper realizes the multi-output truncated difference circuits using current mode CMOS, and presents the algorithm designing multi - valued logic functions of a given multivalued truth tables. This algorithm divides the discrete valued functions and the interval functions, and transforms them into the truncated difference functions. The transformed functions are realized by current mode CMOS. The technique presented here is applied to MOD4 addition circuit and GF(4) multiplication circuit.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.949-952
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• 2000

A low power 10bit current-mode folding and interpolating CMOS analog to digital converter (ADC) with arithmetic folding blocks is presented in this paper. A current-mode two-level folding amplifier with a high folding rate (FR) is designed not only to prevent ADC from increasing a FR excessively, but also to perform a high resolution at a single power supply of 3.3V The proposed ADC is implemented by a 0.6${\mu}$m n-well CMOS single poly/double metal process. The simulation result shows a differential nonlinearity (DNL) of ${\pm}$0.5LSB, an integral nonlinearity (INL) of ${\pm}$1.0LSB

• 한국전자통신학회논문지
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• 제8권10호
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• pp.1477-1483
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• 2013

연속시간 전류모드 기저대역 채널선택 필터 설계를 위하여 전류이득과 단위이득 주파수를 개선시킨 저전압 선형 캐스코드 전류모드 적분기를 제안하였다. 제안된 전류모드 적분기는 CMOS 상보형 회로로 구성된 완전 차동 형태의 입 출력단으로 구성하였으며, 여기에 캐스코드 트랜지스터를 추가시킴으로써 바이어스 단을 구성하여 선형영역에서 동작시켜 저전압 구조에 적합하도록 설계하였다. 이 때 바이어스 전압을 선택적으로 제어하여 주파수 대역이 가변될 수 있도록 설계하였다. 시뮬레이션 결과를 통해 설계한 선형 캐스코드 전류모드 적분기가 저전압 동작, 전류 이득 및 단위이득 주파수 등 모두 만족할 만한 특성을 가지고 있음을 확인하였다.

• 한국전기전자재료학회논문지
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• 제23권4호
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• pp.267-272
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• 2010

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.457-458
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• 2008

This paper presents an output common mode current compensation method to achieve both constant Gm and constant gain. A conventional rail-to-rail CMOS op-amp with constant Gm was designed by using complementary differential input stage and current compensation skills. But it doesn't operate constant gain, because of output resistance variation. With $0.18{\mu}m$ CMOS process, the simulation results show that the differential gain variation can achieve less than 1.3dB. And a 60dB gain, a 13.5MHz unity gain-frequency, and 1mW power consumption, when operating at 1.8V and 10pF load.