• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
• /
• pp.1006-1007
• /
• 2006

An active-clamp current-fed push-pull converter for the step-up application is proposed. The proposed converter is composed of active-clamp circuits and a voltage doubler rectifier. Thus, the voltage stress of the main switches is reduced and the output diodes are clamped to output voltage. Moreover, the output diodes can achieve zero current switching (ZCS) by the series resonance between resonant capacitors and leakage inductances. The prototype is designed for 350V/1.5kW with input voltage range $30{\sim}60V$. The theoretical analysis and experimental results are presented.

• Journal of Power Electronics
• /
• 제12권2호
• /
• pp.249-257
• /
• 2012

An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
• /
• 제13권1호
• /
• pp.20-30
• /
• 2013

This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
• /
• 제49권8호
• /
• pp.551-556
• /
• 2000

A zero-voltage-switching(ZVS) programmable power supply employing the ZVS active clamp forward converter is suggested. Through the analysis on operation region of the supply, the constant power region and the maximum current limit region are clearly identified. Furthermore, the duty ratio range corresponding to the variation range of the output voltages and the control scheme at the minimum duty ration region are presented. Finally, in order to vefity the validity of the operation for the proposed power supply, experimental evaluation results obtained on an 1kW prototype power supply for the 198~242VAC input voltage range(220VAC$\pm$10%), the 0~25V output voltage range, and the 100kHz switching frequency are presented.

• Journal of Power Electronics
• /
• 제9권1호
• /
• pp.18-25
• /
• 2009

Conventional series-resonant pulse frequency modulation controlled DC-DC high power converters with a high-frequency transformer link which is designed for driving the high power microwave generator has the problem of hard switching commutation at turn-on and turn-off of active power switching devices. This problem is due to the influence of the magnetizing current of the high-frequency transformer. This paper presents a novel prototype for a high-frequency transformer using parasitic parameters with a lossless inductive snubber and a series resonant capacitor assisted series-resonant zero current switching pulse frequency modulated DC-DC power converter, which is designed using a high power magnetron for microwave ovens. In order to implement a complete and efficient soft switching commutation, the performance of the new converter topology is practically confirmed and evaluated in the prototype of a power microwave generator.

• 반도체디스플레이기술학회지
• /
• 제20권2호
• /
• pp.29-33
• /
• 2021

A 5.8-GHz 1W wireless power transmission system was used for charging a smart phone. The voltage of one RF power receiver with antenna was not enough for charging. Several power receivers for charging a smart phone was connected serially. The voltage of several RF power receivers are highly enough for charging a smart phone within 50cm. However, the lack of current from small capacitances of RF-DC converters is not suitable for charging smart phone. It means very long charging time. In this paper, the voltage multiplier circuits for RF-DC converters were analyzed to increase the current and voltage at the same time to reduce the charging time in smartphone RF wireless charging. Through the analysis of multiplier circuits, the 7-stage parallel multiplier circuit with voltage-doubler units are suitable for charging the smartphone, which supplies 5V and 700mA at 3V@5.8GHz.

• 한국전자파학회논문지
• /
• 제21권6호
• /
• pp.670-680
• /
• 2010

본 논문에서는 0.13 ${\mu}m$ CMOS 공정을 사용하여, 이동단말기 탑재에 적합한 저 전력, 저 잡음 구조 개별 소자 (LNA, Mixer, VCO, frequency doubler, signal generator, down converter)들을 제안하고, 나아가 이를 하나의 칩으로 집적화 시킨 60 GHz 단일 칩 수신기 구조를 제안한다. 저전력화를 위해 current re-use 구조를 적용시킨 LNA의 경우, 11.6 mW 의 전력 소모 시, 56 GHz부터 60 GHz까지 측정된 잡음지수(NF)는 4 dB 이하이다. 저전력화를 위한 resistive mixer의 경우, Cgs의 보상 회로를 통하여 낮은 LO 신호 크기에서도 동작 가능하도록 하였다. -9.4dB의 변환 이득을 보여주며, 20 dB의 LO-RF isolation 특성을 가진다. Ka-band VCO는 4.99 mW 전력 소모 시측정된 출력 신호 크기는 27.4 GHz에서 -3 dBm이 되며, 26.89 GHz에서부터 1 MHz offset 기준으로 -113 dBc/Hz의 phase noise 특성을 보인다. 49.2 dB의 원신호 억제 효과를 보이는 Frequency Doubler는 총 전력 소모가 9.08 mW일 경우, -4 dBm의 27.1 GHz 입력 신호 인가 시 -53.2 dBm의 fundamental 신호(27.1 GHz)와 -4.45dBm의 V-band second harmonic 신호(54.2 GHz)를 얻을 수 있었으며, 이는 -0.45 dB의 변환 이득을 나타낸다. 60 GHz CMOS 수신기는 LNA, resistive mixer, VCO, frequency doubler, 그리고 drive amplifier로 구성되어 있으며, 전체 전력 소모는 21.9 mW이다. WLAN과의 호환 가능성을 위하여, IF(Intermediate Frequency) bandwidth가 5.25GHz(4.75~10 GHz)이며, RF 3 dB bandwidth는 58 GHz를 중심으로 6.2 GHz이다. 이때의 변환 손실은 -9.5 dB이며, 7 dB의 NF와 -12.5 dBm의 높은 입력 P1 dB를 보여주고 있다. 이는 60 GHz RF 회로의 저전력화, 저가격화, 그리고 소형화를 통한 WPAN용 이동단말기의 적용 가능성을 입증한다.

• Journal of Power Electronics
• /
• 제15권4호
• /
• pp.1131-1138
• /
• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• 전력전자학회논문지
• /
• 제21권3호
• /
• pp.224-230
• /
• 2016

In this study, a single-power-conversion series-resonant ac-dc converter with high efficiency and high power factor is proposed. The proposed ac-dc converter consists of single-ended primary-inductor converter with an active-clamp circuit and a voltage doubler with series-resonant circuit. The active-clamp circuit clamps the surge voltage and provides zero-voltage switching of the main switch. The series-resonant circuit consists of leakage inductance $L_{lk}$ of the transformer and resonant capacitors $ C_{r1}$ and $ C_{r2}$. This circuit also provides zero-current switching of output diodes $D_1$ and $D_2$. Thus, the switching loss of switches and reverse-recovery loss of output diodes are considerably reduced. The proposed ac-dc converter also achieves high power factor using the proposed control algorithm without the addition of a power factor correction circuit and a dc-link electrolytic capacitor. A detailed theoretical analysis and the experimental results for a 1kW prototype are discussed.

• 한국항행학회논문지
• /
• 제15권4호
• /
• pp.596-601
• /
• 2011

본 논문에서는 간단한 회로구조와 높은 효율을 갖는 스위칭 방식의 E급 주파수 체배기에 대한 연구를 수행하였다. 주파수 체배는 능동소자의 비선형성에 의해 발생하는데 본 논문에서는 FET 능동소자를 간단한 스위치 및 기생소자 성분 모델로 근사하여 특성을 해석하고자 하였다. FET를 입력에 의해 동작하는 스위치 및 기생소자로 모델링하고 E급 주파수 체배기의 정합소자 값을 유도하였다. ADS시뮬레이터를 이용하여 출력 전압과 전류 파형 및 효율을 시뮬레이션하고 기생성분에 따른 변화를 연구하였다. 기생 커패시턴스, 저항, 인덕턴스에 의한 영향을 시뮬레이션하였으며 입력주파수 2.9GHz, 바이어스전압 2V일 때, 출력주파수 5.8GHz에서 기생커패시턴스가 0pF에서 1pF으로 변화함에 따라 드레인효율은 98%에서 28%로 감소하여 기생커패시턴스 CP가 FET의 기생 성분 중 가장 큰 영향을 끼친 것을 확인했다.