• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.10-21
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• 1999

This paper describes a 12bit CMOS current cell matrix D/A converter which shows a conversion rate of 65MHz and a power supply of 3.3V. Designed D/A converter utilizes current cell matrix structure with good monotonicity characteristic and fast settling time, and it is implemented by using the tree structure bias circuit, the symmetrical routing method with ground line and the cascode current switch to reduce the errors of the conventional D/A converter caused by a threshold voltage mismatch of current cells and a voltage drop of the ground line. The designed D/A converter was implemented with a $0.6{\mu}m$ CMOS n-well technology. The measured data shows a settling time of 20ns, a conversion rate of 50 MHz and a power dissipation of 35.6mW with a single power supply of 3.3V. The experimental SNR, DNL, and INL of the D/A converter is measured to be 55dB, ${\pm}0.5LSB$, and ${\pm}2LSB$, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.91-97
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• 2013

In this paper, a current steering 10-bit CMOS D/A converter to drive a NTSC/PAL analog TV is proposed. The proposed D/A converter has a 50MS/s operating speed with a 6+4 segmented type. Further, in order to minimize the device mismatch, a self-calibration bias technique with a fully integrated termination resistance is discussed. The chip has been fabricated with a 3.3V 0.11um 1-poly 6-metal CMOS technology. The effective chip area is $0.35mm^2$ and power consumption is about 88mW. The experimental result of SFDR is 63.1dB, when the input frequency is 1MHz at the 50MHz of sampling frequency.

• Clinics in Orthopedic Surgery
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• v.10 no.4
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• pp.407-412
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• 2018

Background: We conducted this study to determine the optimal length of patellar and tibial bone blocks for the modified transtibial (TT) technique in anterior cruciate ligament (ACL) reconstruction using the bone-patellar tendon-bone (BPTB) graft. Methods: The current single-center, retrospective study was conducted in a total of 64 patients with an ACL tear who underwent surgery at our medical institution between March 2015 and February 2016. After harvesting the BPTB graft, we measured its length and that of the patellar tendon, patellar bone block, and tibial bone block using the arthroscopic ruler and double-checked measurements using a length gauge. Outcome measures included the length of tibial and femoral tunnels, inter-tunnel distance, length of the BPTB graft, patellar tendon, patellar bone block, and tibial bone block and graft-tunnel length mismatch. The total length of tunnels was defined as the sum of the length of the tibial tunnel, inter-tunnel distance and length of the femoral tunnel. Furthermore, the optimal length of the bone block was calculated as (the total length of tunnels - the length of the patellar tendon) / 2. We analyzed correlations of outcome measures with the height and body mass index of the patients. Results: There were 44 males (68.7%) and 20 females (31.3%) with a mean age of 31.8 years (range, 17 to 65 years). ACL reconstruction was performed on the left knee in 34 patients (53%) and on the right knee in 30 patients (47%). The optimal length of bone block was 21.7 mm (range, 19.5 to 23.5 mm). When the length of femoral tunnel was assumed as 25 mm and 30 mm, the optimal length of bone block was calculated as 19.6 mm (range, 17 to 21.5 mm) and 22.1 mm (range, 19.5 to 24 mm), respectively. On linear regression analysis, patients' height had a significant correlation with the length of tibial tunnel (p = 0.003), inter-tunnel distance (p = 0.014), and length of patellar tendon (p < 0.001). Conclusions: Our results indicate that it would be mandatory to determine the optimal length of tibial tunnel in the modified TT technique for ACL reconstruction using the BPTB graft. Further large-scale, multi-center studies are warranted to establish our results.

• Journal of Yeungnam Medical Science
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• v.39 no.2
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• pp.141-149
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• 2022

Background: The present study evaluated the clinical implications of adjuvant chemotherapy according to the mismatch repair (MMR) status and clinicopathologic features of patients with intermediate- and high-risk stage II colon cancer (CC). Methods: This study retrospectively reviewed 5,774 patients who were diagnosed with CC and underwent curative surgical resection at Kyungpook National University Chilgok Hospital. The patients were enrolled according to the following criteria: (1) pathologically diagnosed with primary CC; (2) stage II CC classified based on the 7th edition of the American Joint Committee on Cancer staging system; (3) intermediate- and high-risk features; and (4) available test results for MMR status. A total of 286 patients met these criteria and were included in the study. Results: Among the 286 patients, 54 (18.9%) were identified as microsatellite instability-high (MSI-H) or deficient MMR (dMMR). Although all the patients identified as MSI-H/dMMR showed better survival outcomes, T4 tumors and adjuvant chemotherapy were identified as independent prognostic factors for survival. For the intermediate-risk patients identified as MSI-low (MSI-L)/microsatellite stable (MSS) or proficient MMR (pMMR), adjuvant chemotherapy exhibited a significantly better disease-free survival (DFS) but had no impact on overall survival (OS). Oxaliplatin-containing regimens showed no association with DFS or OS. Adjuvant chemotherapy was not associated with DFS in intermediate-risk patients identified as MSI-H/dMMR. Conclusion: The current study found that the use of adjuvant chemotherapy was correlated with better DFS in MSI-L/MSS or pMMR intermediate-risk stage II CC patients.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.2
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• pp.106-113
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• 2006

Electrical properties of $Si_{0.88}Ge_{0.12}(C)$ p-MOSFETs have been exploited in an effort to investigate $Si_{0.88}Ge_{0.12}(C)$ channel structures designed especially to suppress diffusion of dopants during epitaxial growth and subsequent fabrication processes. The incorporation of 0.1 percent of carbon in $Si_{0.88}Ge_{0.12}$ channel layer could accomodate stress due to lattice mismatch and adjust bandgap energy slightly, but resulted in deteriorated current-voltage properties in a broad range of operation conditions with depressed gain, high subthreshold current level and many weak breakdown electric field in gateoxide. $Si_{0.88}Ge_{0.12}(C)$ channel structures with boron delta-doping represented increased conductance and feasible use of modulation doped device of $Si_{0.88}Ge_{0.12}(C)$ heterostructures.

• Progress in Superconductivity and Cryogenics
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• v.16 no.4
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• pp.49-52
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• 2014

REBCO coated conductor (CC) tapes with superior mechanical and electromechanical properties are preferable in applications such as superconducting coils and magnets. The CC tapes should withstand factors that can affect their performance during fabrication and operation of its applications. In coil applications, CC tapes experience different mechanical constraints such as tensile or compressive stresses. Recently, the critical current ($I_c$) degradation of CC tapes used in coil applications due to delamination were already reported. Thermal cycling, coefficient of thermal expansion mismatch among constituent layers, screening current, etc. can induce excessive transverse tensile stresses that might lead to the degradation of $I_c$ in the CC tapes. Also, CC tapes might be subjected to very high magnetic fields that induce strong Lorentz force which possibly affects its performance in coil applications. Hence, investigation on the delamination mechanism of the CC tapes is very important in coiling, cooling, operation and design of prospect applications. In this study, the electromechanical properties of REBCO CC tapes fabricated by reactive co-evaporation by deposition and reaction (RCE-DR) under transversely applied loading were investigated. Delamination strength of the CC tape was determined using the anvil test. The $I_c$ degraded earlier under transverse tensile stress as compared to that under compressive one.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.499-500
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• 2006

This paper presents a fast switching CMOS frequency synthesizer with a new coarse tuning method for PHS applications. To achieve the fast lock-time and the low phase noise performance, an efficient bandwidth control scheme is proposed. Charge pump up/down current mismatches are compensated with the current mismatch compensation block. Also, the proposed coarse tuning method selects the optimal tuning capacitances of the LC-VCO to optimize the phase noise and the lock-time. The measured lock-time is about $20{\mu}s$. This chip is fabricated with $0.25{\mu}m$ CMOS technology, and the die area is $0.7mm{\times}2.1mm$. The power consumption is 54mW at 2.7V supply voltage.

• Journal of the Korean Magnetics Society
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• v.17 no.6
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• pp.246-252
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• 2007

This paper describes the effect of the mixing ratio of starting materials and the growth parameters of magnetic garnet films by LPE on the properties of the films and suggests the conditions to obtain the films suitable for the Faraday rotators of the optical CTs. The properties of the films investigated for the evaluation of the films were thickness, surface morphology, X-ray diffraction, lattice constant, lattice mismatch between film and substrate (single crystal nonmagnetic wafer), and Faraday rotation angle. Optical CTs have been fabricated and evaluated using the films grown.

• Journal of Environmental Impact Assessment
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• v.23 no.1
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• pp.1-9
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• 2014

This study, focusing on the area expansion of limestone mines, identifies the problems of Environmental Impact Assessment(EIA) and what impact the current problems exert on another mines developing process. The legal relations analysis reveals that the Management of Mountainous Districts Act and other related laws effect on EIA process, especially the case of area expansion of limestone mines excluded from EIA. However, these problems can create mismatch with the policy goal of EIA system and have a negative impact on the environment in the future. A series of indepth interviews with managers in related agencies found that those agencies have been unaware of the seriousness of the problem. Without any strategy, negative result made by development activities would get more serious and sustainable development may not be possible at all. In order to solve these problems, government should modify the current interdependent legal provision and create the incentive structure to participate actively related agency in the EIA system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.370-377
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• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.