• Journal of Korean Society of Transportation
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• v.30 no.2
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• pp.67-78
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• 2012

The current traffic regulations in Korea stipulate that traffic should keep to the right according to the Road Traffic Act; thus, customarily, the 'seat-on-the-left' system has been maintained. However, an increased number of 'seat-on-the-right' vehicles are being imported via a variety of routes from foreign countries, especially from Japan. According to the data from July 2004, 1,343 cargo vehicles and 593 passenger vehicles (for diplomats, etc.) were currently being driven on domestic road. As these 'seat-on-the-right' vehicles are not compatible with the domestic transportation system of driving on the right side of the road, there is a high risk of accidents. Experiments show that such system-driver mismatch causes longer operation time for directional signals, higher error frequency in yielding due to additional mental adjustments for 'seat-on-the-right' vehicle drivers. These are, therefore, influential factors which can lead to possible accidents. Furthermore, when the experiments test the visual range during overtaking maneuvers, the visual range of the drivers in the 'seat-on-the-left' vehicle was 2.95 meters as opposed to 1.7 meters for the drivers in the 'seat-on-the-right' vehicle. (In the experiment, the drivers were instructed to look at the paper cup 10 meters away from the back of drivers' seat.) The results demonstrate that it is necessary to have additional safety measures be implemented for the 'seat-on-the-right' vehicles.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.19 no.6
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• pp.163-179
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• 2020

With the expansion of platform-based taxi service, mobility and convenience of users are getting better. However, due to profitability problem, marginalized areas in the supply of the service are expected to appear. As such, this study analyzed spatial marginalization of taxi service caused by imbalance in supply and demand during the night-time when public transportation service is suspended. According to hot-spot analysis of taxi, outskirt of a city and residential areas showed high vacancy and greater number of drop-offs compared to the number of pick-ups. On the contrary, they were confirmed low in the center and sub-centers of a city. Centrality analysis also showed a similar pattern with hot-spot analysis. Due to this, drivers may refuse to pick up a customer bound for an area with lower out-degree centrality compared to in-degree centrality as it might be difficult for the drivers to pick up another customer after dropping off the current customer. Thus, customers may need to wait for a taxi for a longer time. For this reason, improvement in spatial marginalization caused by mismatch of supply and demand is required. Also, the outcome of this study is expected to be utilized as a basic data.

• Korean Journal of Cognitive Science
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• v.34 no.1
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• pp.39-66
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• 2023

New media moved the place of social exchange to the Internet, allowing large groups to communicate in one place beyond the limits of time and space. Recent studies have also reported cases in which human social abilities do not keep up with the expansion of group scale through social media. In this context, current study investigated how human perception of social information is affected by the expansion of the group scale in the context of majority bias. Using Internet-based task, the psychological processes that group ratio and group size are perceived and affect majority-biased social information use were investigated, and whether group scale moderates those processes was examined. The group ratio has a positive effect on the majority bias, and the relationship was partially mediated by ratio perception. Group scale did not moderate the relationship between group ratio and ratio perception. On the other hand, the correlation between group size and majority-biased social information use was not significant. Group scale moderates group size perception. The group size and size perception showed positive correlation under the smaller group scale condition. However under the extended group scale condition, the perceived group size became significantly lower and lost its correlation with group size. These results provide evidence that the psychological mechanism related to group size perception was not properly responding to the expansion of the group scale. Furthermore, the possibility of a specific psychological mechanism for processing group size information and the form of information input specifically accepted by majority bias were discussed from perspective of evolutionary psychology.

• The Transactions of the Korea Information Processing Society
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• v.13 no.6
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• pp.284-290
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• 2024

Speech emotion recognition (SER) is a technique that is used to analyze the speaker's voice patterns, including vibration, intensity, and tone, to determine their emotional state. There has been an increase in interest in artificial intelligence (AI) techniques, which are now widely used in medicine, education, industry, and the military. Nevertheless, existing researchers have attained impressive results by utilizing acted-out speech from skilled actors in a controlled environment for various scenarios. In particular, there is a mismatch between acted and spontaneous speech since acted speech includes more explicit emotional expressions than spontaneous speech. For this reason, spontaneous speech-emotion recognition remains a challenging task. This paper aims to conduct emotion recognition and improve performance using spontaneous speech data. To this end, we implement deep learning-based speech emotion recognition using the VGG (Visual Geometry Group) after converting 1-dimensional audio signals into a 2-dimensional spectrogram image. The experimental evaluations are performed on the Korean spontaneous emotional speech database from AI-Hub, consisting of 7 emotions, i.e., joy, love, anger, fear, sadness, surprise, and neutral. As a result, we achieved an average accuracy of 83.5% and 73.0% for adults and young people using a time-frequency 2-dimension spectrogram, respectively. In conclusion, our findings demonstrated that the suggested framework outperformed current state-of-the-art techniques for spontaneous speech and showed a promising performance despite the difficulty in quantifying spontaneous speech emotional expression.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.4
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• pp.135-140
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• 2024

It is said that PV power generation systems have a long lifespan compared to other renewable energy sources and require little maintenance. However, there are cases where the performance expected during initial design is not achieved due to shading, temperature rise, mismatch, contamination/deterioration of PV modules, failure of inverter, leakage current, and arc generation. Therefore, in order to solve the problems of these systems, the power generation amount and operation status are investigated qualitatively, or the performance is comparatively analyzed based on the performance ratio (PR), which is the performance index of the solar power generation system. However, because it includes large losses, it is difficult to accurately determine whether there are any abnormalities such as performance degradation, failure, or defects in the PV power generation system using only the performance coefficient. In this paper, we studied a status diagnosis algorithm for shading, inverter failure, leakage, and arcing of PV modules to optimize the power generation of PV power generation systems according to changes in the surrounding environment. In addition, using the studied algorithm, we examined the results of an empirical test on condition diagnosis for each area and the resulting optimized operation of power generation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.48-57
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• 2006

This work describes a 12b 200KHz 0.52mA $0.47mm^2$ algorithmic ADC for sensor applications such as motor controls, 3-phase power controls, and CMOS image sensors simultaneously requiring ultra-low power and small size. The proposed ADC is based on the conventional algorithmic architecture with recycling techniques to optimize sampling rate, resolution, chip area, and power consumption. The input SHA with eight input channels for high integration employs a folded-cascode architecture to achieve a required DC gain and a sufficient phase margin. A signal insensitive 3-D fully symmetrical layout with critical signal lines shielded reduces the capacitor and device mismatch of the MDAC. The improved switched bias power-reduction techniques reduce the power consumption of analog amplifiers. Current and voltage references are integrated on the chip with optional off-chip voltage references for low glitch noise. The employed down-sampling clock signal selects the sampling rate of 200KS/s or 10KS/s with a reduced power depending on applications. The prototype ADC in a 0.18um n-well 1P6M CMOS technology demonstrates the measured DNL and INL within 0.76LSB and 2.47LSB. The ADC shows a maximum SNDR and SFDR of 55dB and 70dB at all sampling frequencies up to 200KS/s, respectively. The active die area is $0.47mm^2$ and the chip consumes 0.94mW at 200KS/s and 0.63mW at 10KS/s at a 1.8V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.46-55
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• 2016

This work proposes a 13b 100MS/s 45nm CMOS ADC with a high dynamic performance for IF-domain high-speed signal processing systems based on a four-step pipeline architecture to optimize operating specifications. The SHA employs a wideband high-speed sampling network properly to process high-frequency input signals exceeding a sampling frequency. The SHA and MDACs adopt a two-stage amplifier with a gain-boosting technique to obtain the required high DC gain and the wide signal-swing range, while the amplifier and bias circuits use the same unit-size devices repeatedly to minimize device mismatch. Furthermore, a separate analog power supply voltage for on-chip current and voltage references minimizes performance degradation caused by the undesired noise and interference from adjacent functional blocks during high-speed operation. The proposed ADC occupies an active die area of $0.70mm^2$, based on various process-insensitive layout techniques to minimize the physical process imperfection effects. The prototype ADC in a 45nm CMOS demonstrates a measured DNL and INL within 0.77LSB and 1.57LSB, with a maximum SNDR and SFDR of 64.2dB and 78.4dB at 100MS/s, respectively. The ADC is implemented with long-channel devices rather than minimum channel-length devices available in this CMOS technology to process a wide input range of $2.0V_{PP}$ for the required system and to obtain a high dynamic performance at IF-domain input signal bands. The ADC consumes 425.0mW with a single analog voltage of 2.5V and two digital voltages of 2.5V and 1.1V.