• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.825-828
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• 2005

In this paper, we propose a new nonvolatile unit memory cell and proposal peripheral circuit using the polymer material. Memory that relies on bistable behavior- having tow states associated with different resistances at the same applied voltage - has attracted much interest because of its nonvolatile properties. Such memory may also have other merits, including simplicity of structure and manufacturing, and the small size of memory cells. We have plotted the load line graphs for the use of a polymer memory character, hence we have designed in the band-gap reference shape of a write/erase drive, and then designed in the 2-stage differential amplifier shape of a sense amplifier in the consideration of a low current characteristic of a polymer memory cell. The simulation result shows that is has high gain about 80dB by sensing the very small current.

• Journal of Computing Science and Engineering
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• 제3권3호
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• pp.181-194
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• 2009

Flash memory is increasingly being used in a wide range of storage applications because of its low power consumption, low access latency, small form factor, and high shock resistance. However, the current platforms for flash memory software development do not meet the ever-increasing requirements of flash memory applications. This paper presents three different hardware platforms for flash memory/NVRAM (non-volatile RAM) software development that overcome the limitations of the current platforms. The three platforms target different types of host system and provide various features that facilitate the development and verification of flash memory/NVRAM software. In this paper, we also demonstrate the usefulness of the three platforms by implementing three different types of storage system (one for each platform) based on them.

• 한국전자통신학회논문지
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• 제11권2호
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• pp.159-164
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• 2016

무선통신시스템은 한정된 에너지를 갖는 배터리를 사용하기 때문에 저전력 회로로 구현되어야 하며, 이를 위하여 주파수와 상관없이 일정한 전력을 나타내는 전류모드 회로가 연구되어왔다. 본 논문에서는 초저전력 동작이 가능하도록 Dynamic Voltage Scaling 전원을 유도하며, 전류모드 신호처리 중 메모리 동작에서 저장된 에너지가 누설되는 Clock-Feedthrough 문제를 최소화하는 전류메모리 회로를 제안한다. $0.35{\mu}m$ 공정의 BSIM3 모델로 Near-threshold 영역의 전원 전압을 사용한 시뮬레이션을 진행한 결과, 1MHz의 스위칭 동작에서 $2{\mu}m$의 메모리 MOS Width, $0.3{\mu}m$의 스위치 MOS Width, $13{\mu}m$의 Dummy MOS Width로 설계할 때, Clock-Feedthrough의 영향을 최소화시킬 수 있었으며 1.2V의 Near-threshold 전원전압에서 소비전력은 $3.7{\mu}W$가 계산되었다.

• ETRI Journal
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• 제30권3호
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• pp.483-485
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• 2008

A micro-sensor network is comprised of a large number of small sensors with limited memory capacity. Current key-establishment schemes for symmetric encryption require too much memory for micro-sensor networks on a large scale. In this paper, we propose a memory-efficient hypercube key establishment scheme that only requires logarithmic memory overhead.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.363-369
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• 2017

Phase-change random access memory (PRAM) has been emerged as a potential memory due to its excellent scalability, non-volatility, and random accessibility. But, as the cell current is reducing due to cell size scaling, the read-sensing window margin is also decreasing due to increased variation of cell performance distribution, resulting in a substantial loss of yield. To cope with this problem, a novel adaptive read-sensing reference current generation scheme is proposed, whose trimming range and resolution are adaptively controlled depending on process conditions. Performance evaluation in a 58-nm CMOS process indicated that the proposed read-sensing reference current scheme allowed the integral nonlinearity (INL) to be improved from 10.3 LSB to 2.14 LSB (79% reduction), and the differential nonlinearity (DNL) from 2.29 LSB to 0.94 LSB (59% reduction).

• Journal of Advanced Marine Engineering and Technology
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• 제31권4호
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• pp.410-416
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• 2007

PRAM (Phase change random access memory) is one of the most promising candidates for next generation non-volatile memories. However, the high reset current is one major obstacle to develop a high density PRAM. One way of the reset current reduction is to change the heater electrode material. In this paper, to reduce the reset current for phase transition, we have investigated the effect of heater electrode material parameters using finite element analysis. From the simulation. the reset current of PRAM cell is reduced from 2.0 mA to 0.72 mA as the electrical conductivity of heater is decreased from $1.0{\times}10^6\;(1/{\Omega}{\cdot}m$) to $1.0{\times}10^4\;(1/{\Omega}{\cdot}m$). As the thermal conductivity of heater is decreased, the reset current is slightly reduced. But the reset current of PRAM cell is not changed as the specific heat of heater is changed.

• 한국전기전자재료학회논문지
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• 제29권7호
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• pp.400-403
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• 2016

The resistive memory switching characteristics of resistive random access memory (ReRAM) using the amorphous GeSe thin film have been demonstrated at Al/Ti/GeSe/$n^+$ poly Si structure. This ReRAM indicated bipolar resistive memory switching characteristics. The generation and the recombination of chalcogen cations and anions were suitable to explain the bipolar switching operation. Space charge limited current (SCLC) model and Poole-Frenkel emission is applied to explain the formation of conductive filament in the amorphous GeSe thin film. The results showed characteristics of stable switching and excellent reliability. Through the annealing condition of $400^{\circ}C$, the possibility of low temperature process was established. Very low operation current level (set current: ~ ${\mu}A$, reset current: ~ nA) was showed the possibility of low power consumption. Particularly, $n^+$ poly Si based GeSe ReRAM could be applied directly to thin film transistor (TFT).

• 한국통신학회논문지
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• 제21권5호
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• pp.1325-1331
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• 1996

본 논문에서는 전류 스위칭(switched-current:SI) 시스템에서 THD(total harmonic distortion) 증가 원인인 클럭피드스루(clock feedthrough:CFT) 오차 전압을 감소시키는 새로운 전류 메모리(current-memory) 회로를 제안하였다. 제안한 전류 메모리는 CMOS 상보형의 PMOS 트랜지스터를 이용하여 CFT 오차 전압에 의한 출력 왜곡 전류를 감소시킨다. 제안한 전류 메모리 회로를 $1.2{\mu}{\textrm{m}}$ CMOS 공정을 사용하여 설계하고, 입력으로 전류 크기 $68{\mu}{\textrm{m}}$인 1MHz 정현파 신호를 인가하였다.(샘플링 주파수:20MHz) 모의 실험 결과, 기존의 전류 메모리보다 CFT 오차 전압에 의한 출력 왜곡 전류가 10배 정도 감소를 나타내었으며 신호 대 바이어스 전류비가 0.5(peak signal-to-bias current ratio:i/J)인 1KHz 신호를 인가할 경우 THD는 -57dB이다.

• 한국정밀공학회지
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• 제20권1호
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• pp.43-49
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• 2003

In this study, micro electrochemical machining method was introduced for accomplishment the fabrication technology of functional parts and smart structures using the Ni-Ti shape memory alloy. From the experimental result, the micro part which has very fine surface could be achieved by use of micro electrochemical process with point electrode method. Concretely, the optimal performance of micro electrochemical process in Ni-Ti SMA was obtained at the condition of approximately 100% of current efficiency and high frequency pulse current. That is, much finer surface integrity and shape memory effect can be obtained at the same condition mentioned above.

• 한국경영과학회:학술대회논문집
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• 한국경영과학회 2008년도 추계학술대회 및 정기총회
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• pp.236-246
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• 2008

We consider the Inventory Routing problem(IRP) for the vending machine operating system. An artificial immune system(AIS) is introduced to solve the IRP. The IPR is an rolling wave planning. The previous solution of IRP is one of good initial solution of current IRP. We introduce an Artificial Immune system with memory cell (AISM) which store previous solution in memory cell and use an initial solution for current problem. Experiment results shows that AISM reduced calculations time in relatively less demand uncertainty.