• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.510-510
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• 2000

This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.1
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• pp.6-13
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• 2008

National standard system for calibrating current transformer(CT) up to primary current of 20,000A have been established. The system consists of 20,000 A AC high current source, CT comparator, standard CT, CT under test and CT burden. An AC high current is applied tn the primary windings of both the standard CT and the CT under test, and then the CT comparator measures the ratio error and the phase displacement by comparing the secondary currents of the two transformers. As a validity check for 20,000 A CT calibration system, the comparison with the two national standard institutes(NMIs) has been performed using same CTs. The comparison results of the CTs are consistent with those measured at two NMIs within 0.004 % for ratio error and 0.1 min for phase displacement in the primary current ranges of Ip = 10 - 20,000 A with a secondary current of Is = 5 A.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.11
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• pp.2009-2014
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• 2017

A novel structure of phase locked loop (PLL) with a time constant comparator and a current compensator has been proposed. The proposed PLL uses small capacitors which are impossible for stable operation in a conventional PLL. It is small enough to be integrated into a single chip. The time constant comparator detects the loop filter output voltage variations using signals which are passed through small and large RC time constants. The signal from the large RC time constant node is the average of the loop filter output voltage. The output voltage of another node is approximately equal to the present loop filter voltage. The output of the time constant comparator controls a current compensator and charge/discharge small size loop filter capacitors. It makes the proposed PLL operate stably. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1091-1097
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• 2013

This paper presents a rectifier with comparator using unbalanced body biasing in $0.11{\mu}m$ RF CMOS process. It is composed of MOSFETs and two comparators. The comparator is used to reduce reverse leakage current which occurs when the load voltage is higher than input voltage. For the comparator, unbalanced body biasing is devised. By using unbalanced body biasing, reference voltage for comparator changing from high state to low state is increased, and it reduces time interval for leakage current to flow. 13.56 MHz 2 Vpp signal is used for input and $1k{\Omega}$ resistor and 1 nF capacitor are used for output load for simulation and experimental environment. In simulation environment, voltage conversion efficiency(VCE) is 87.5 % and Power conversion efficiency(PCE) is 50 %. When the rectifier is measured, VCE shows 90.203 % and PCE shows 45 %.

• Journal of IKEEE
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• v.25 no.1
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• pp.206-211
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• 2021

This paper proposes a Self-Reset Zero-Current Switching (ZCS) Circuit for thermoelectric energy harvesting. The Self-Reset ZCS circuit minimizes the operating current consumed by the voltage comparator, thereby reduces the power consumption of the energy harvesting circuit and improves the energy conversion efficiency by adding the self-reset function to the comparator. The Self-Reset ZCS circuit shows 3.4% of improvement in energy efficiency compared to the energy harvesting system with the conventional analog comparator ZCS for the output/input voltage ratio of 5.5 as a result of circuit simulation. The proposed circuit is useful for improving the performance of the wearable and bio-health-related harvesting circuits, where low-power and energy-efficient thermoelectric energy harvesting is needed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.421-425
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• 2008

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.5
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• pp.250-256
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• 2006

Both ratio error and phase angle error in current transformer(CT) depend critically on values of CT burden. Thus, precise measurement of CT burden is very important for the evaluation of CT. A method for the measurement of CT burden has been developed by employing the portable shunt precise resistor with negligible AC-DC resistance difference less than $10^{-5}$. The burden value(value and power factor) can be calculated from resistance and reactance obtained by measuring the change of ratio error and phase angle error caused by the change of shunt resistor. The uncertainty for the method is evaluated and found to be abut 2 %.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.8
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• pp.593-600
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• 2010

In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.9-9
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• 2010

In this paper, High Brightness LED driver IC using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses $1{\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre(Cadence) simulation.

• Journal of IKEEE
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• v.20 no.4
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• pp.373-377
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• 2016

This paper presents a low power boost converter using offset controlled Zero Current Sensor (ZCS) control for thermoelectric energy harvesting.[1] [5] Offset controlled ZCS uses adjustable pre-offset that is controled by 6bit code each connected gate of NMOS for switching. Offset controlled ZCS demonstrates an efficiency that is higher than using analog comparator ZCS and that is smaller area than using delay line ZCS. Experimentally, the offset controlled ZCS system consumes 10 times less power than analog comparator ZCS based system at similar performance.