• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.93-94
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• 2005

Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13 ${\mu}m$ technology node. In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge, Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness.

• Bulletin of the Korean Chemical Society
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• v.34 no.3
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• pp.768-772
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• 2013

Layered mixed metal hydroxy double salts (HDS) with the formulas $(Cu_{0.75}Ni_{0.25})_2(OH)_3NO_3$ ((Cu, Ni)-HDS) and $Cu_2(OH)_3NO_3$ ((Cu, Cu)-HDS) were prepared via slow hydrolysis reactions of CuO with $Ni(NO_3)_2$ and $Cu(NO_3)_2$, respectively. The crystal structures, morphologies, bonding natures, and magnetic properties of (Cu, Ni)-HDS and (Cu, Cu)-HDS were characterized with X-ray diffraction (XRD), scanning electron microscopy (SEM), Fourier transformation infrared spectroscopy (FT-IR), thermogravimetric analysis (TGA), and a superconducting quantum interference device (SQUID). Even though (Cu, Ni)-HDS has a similar layered structure to that of (Cu, Cu)-HDS, the bonding nature of (Cu, Ni)-HDS is slightly different from that of (Cu, Cu)-HDS. Therefore, the magnetic properties of (Cu, Ni)-HDS are significantly different from those of (Cu, Cu)-HDS. The origin of the abnormal magnetic properties of (Cu, Ni)-HDS can be explained in terms of the bonding natures of the interlayer and intralayer structures.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.1
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• pp.69-73
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• 2010

Finite-element analyses were conducted to investigate the thermal stress in 3-dimensional stacked wafers package containing through-silicon-via (TSV), which is being widely used for 3-Dimensional integration. With finite element method (FEM), thermal stress was analyzed with the variation of TSV diameter, bonding diameter, pitch and TSV height. It was revealed that the maximum von Mises stresses occurred at the edge of top interface between Cu TSV and Si and the Si to Si bonding site. As TSV diameter increased, the von Mises stress at the edge of TSV increased. As bonding diameter increased, the von Mises stress at Si to Si bonding site increased. As pitch increased, the von Mises stress at Si to Si bonding site increased. The TSV height did not affect the von Mises stress. Therefore, it is expected that smaller Cu TSV diameter and pitch will ensure mechanical reliability because of the smaller chance of plastic deformation and crack initiation.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.4
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• pp.1-8
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• 2022

High-density packaging technologies, including Through-Si-Via (TSV) technologies, are considered important in many fields such as IoT (internet of things), 6G/5G (generation) communication, and high-performance computing (HPC). Achieving high integration in two dimensional packaging has confronted with physical limitations, and hence various studies have been performed for the three-dimensional (3D) packaging technologies. In this review, we described about the causes and effects of scallop formation in TSV, the scallop-free etching technique for creating smooth sidewalls, Cu pillar and Cu-SiO₂ hybrid bonding in TSV. These technologies are expected to have effects on the formation of high-quality TSVs and the development of 3D packaging technologies.

• Transactions on Electrical and Electronic Materials
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• v.6 no.5
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• pp.225-228
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• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• Bulletin of the Korean Chemical Society
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• v.12 no.3
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• pp.276-281
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• 1991

Electrochemical behaviors of optically active sparteine-Cu(II) dihalide complexes were investigated by polarography and cyclic voltammetry (CV). These Cu(II) complexes are rather easier to be reduced to Cu(I) states when comparison is made with other nonplaner copper complexes, We have assigned the CV peaks and polarographic waves related to the redox processes for these complexes. We could also observe the exchange reaction of Cu(II) ion in the complex with mercury metal in the cell having mercury pool. The redox mechanism of these complelxes is as follows; The 1st wave appeared at +0.47 V/+0.65 V corresponds to the reaction of $SpCuX_2+ e{\rightleftarrow}SpCuX_{2^-}$ and the 2nd one at +0.26 V/+0.21 V does the reaction of $SpCuX_{2 ^-} +e{\rightleftarrow}SpCuX_2^{2-}$. The 3rd one at -0.35 V/-0.27 V is dueto the reduction of mercury complex formed via exchange reaction. Where, X is chloride ion.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.129-134
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• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.29-36
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• 2008

In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of $1mm{\times}1mm{\times}700{\mu}m$. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.

• Journal of Sensor Science and Technology
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• v.21 no.1
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• pp.34-38
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• 2012

We have developed a cost effective test socket for ball grid array(BGA) integrated circuit(IC) packages using BeCu metal sheet as a test probe. The BeCu furnishes the best combination of electrical conductivity and corrosion resistance. The probe of the test socket was designed with a BeCu cantilever. The cantilever was designed with a length of 450 ${\mu}m$, a width of 200 ${\mu}m$, a thickness of 10 ${\mu}m$, and a pitch of 650 ${\mu}m$ for $11{\times}11$ BGA. The fabrication of the test socket used techniques such as through-silicon-via filling, bonding silicon wafer and BeCu metal sheet with dry film resist(DFR). The test socket is applicable for BGA IC chip.

• Korean Journal of Materials Research
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• v.24 no.4
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• pp.186-193
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• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.