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http://dx.doi.org/10.4313/TEEM.2005.6.5.225

A Study on the Optimized Copper Electrochemical Plating in Dual Damascene Process  

Yoo, Hae-Young (School of Electrical and Electronics Engineering, Chung-Ang University)
Chang, Eui-Goo (School of Electrical and Electronics Engineering, Chung-Ang University)
Kim, Nam-Hoon (Research Institute of Energy Resources Technology, Chosun University)
Publication Information
Transactions on Electrical and Electronic Materials / v.6, no.5, 2005 , pp. 225-228 More about this Journal
Abstract
In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.
Keywords
Electrochemical plating (ECP); Chemical mechanical polishing (CMP); Step height; Array height; Dishing;
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Times Cited By KSCI : 1  (Citation Analysis)
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