• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.65-71
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• 2007

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of the electroplating current density and the speed of a rotating disc electrode (RDE). Cu filling characteristics into trench vias were improved with increasing the RDE speed. There was a Nernst relationship between half width of trench vias of Cu filling ratio higher than 95% and the minimum RDE speed, and the half width of trenches with 95% Cu filling ratio was linearly proportional to the reciprocal of root of the minimum RED speed.

• Journal of Radiation Protection and Research
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• v.42 no.1
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• pp.63-68
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• 2017

Background: The combined effect of the low energy electron (LEE) irradiation and $Cu^{2+}$ ion on DNA damage was investigated. Materials and Methods: Lyophilized pBR322 plasmid DNA films with various concentrations (1-15 mM) of $Cu^{2+}$ ion were independently irradiated by monochromatic LEEs with 5 eV. The types of DNA damage, single strand break (SSB) and double strand break (DSB), were separated and quantified by gel electrophoresis. Results and Discussion: Without electron irradiation, DNA damage was slightly increased with increasing Cu ion concentration via Fenton reaction. LEE-induced DNA damage, with no Cu ion, was only 6.6% via dissociative electron attachment (DEA) process. However, DNA damage was significantly increased through the combined effect of LEE-irradiation and Cu ion, except around 9 mM Cu ion. The possible pathways of DNA damage for each of these different cases were suggested. Conclusion: The combined effect of LEE-irradiation and Cu ion is likely to cause increasing dissociation after elevated transient negative ion state, resulting in the enhanced DNA damage. For the decrease of DNA damage at around 9-mM Cu ion, it is assumed to be related to the structural stabilization due to DNA inter- and intra-crosslinks via Cu ion.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.17-21
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• 2008

The electroless plating of copper and tin were investigated for the fabrication of Sn-Cu bump. Copper and tin were electroless plated in series on $20{\mu}m$ diameter copper via to form approximately $10{\mu}m$ height bump. In electroless copper plating, acid cleaning and stabilizer addition promoted the selectivity of bath on the copper via. In electroless tin plating, the coating thickness of tin was less uniform relative to that of electroless copper, however the size of Sn-Cu bump were uniform after reflow process.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.79-84
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• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• Journal of Powder Materials
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• v.20 no.4
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• pp.245-252
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• 2013

This study attempted to manufacture a Cu-Ga coating layer via the cold spray process and to investigate the applicability of the layer as a sputtering target material. In addition, changes made to the microstructure and properties of the layer due to annealing heat treatment were evaluated, compared, and analyzed. The results showed that coating layers with a thickness of 520 mm could be manufactured via the cold spray process under optimal conditions. With the Cu-Ga coating layer, the ${\alpha}$-Cu and $Cu_3Ga$ were found to exist inside the layer regardless of annealing heat treatment. The microstructure that was minute and inhomogeneous prior to thermal treatment changed to homogeneous and dense with a more clear division of phases. A sputtering test was actually conducted using the sputtering target Cu-Ga coating layer (~2 mm thickness) that was additionally manufactured via the cold-spray coating process. Consequently, this test result confirmed that the cold sprayed Cu-Ga coating layer may be applied as a sputtering target material.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.63-69
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• 2007

We investigated interconnection processes using Cu vias for MEMS sensor packages. Ag paste layer was formed on a glass substrate and used as a seed layer for electrodeposition of Cu vias after bonding a Si substrate with through-via holes. With applying electrodeposition current densities of $20mA/cm^2\;and\;30mA/cm^2$ at direct current mode to the Ag paste seed-layer, Cu vias of $200{\mu}m$ diameter and $350{\mu}m$ depth were formed successfully without electrodeposition defects. Interconnection processes for MEMS sensor packages could be accomplished with Ti/Cu/Ti line formation, Au pad electrodeposition, Sn solder electrodeposition and reflow process on the Si substrate where Cu vias were formed by Cu electrodeposition into through-via holes.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Carbon letters
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• v.10 no.4
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• pp.305-313
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• 2009

In this study, the adsorption of toxic pollutants onto cetyltrimethylammonium kaolin (CTAB-Kaolin) is investigated. The organo-kaolin is synthesized by exchanging cetyltrimethylammonium cations (CTAB) with inorganic ions on the surface of kaolin. The chemical analysis, the structural and textural properties of kaolin and CTAB-kaolin were investigated using elemental analysis, FTIR, SEM and adsorption of nitrogen at $-196^{\circ}C$. The kinetic adsorption and adsorption capacity of the organo-kaolin towards o-xylene, phenol and Cu(II) ion from aqueous solution was investigated. The kinetic adsorption data of o-xylene, phenol and Cu(II) are in agreement with a second order model. The equilibrium adsorption data were found to fit Langmuir equation. The uptake of o-xylene and phenol from their aqueous solution by kaolin, CTAB-kaolin and activated carbon proceed via physisorption. The removal of Cu(II) ion from water depends on the surface properties of the adsorbent. Onto kaolin, the Cu(II) ions are adsorbed through cation exchange with $Na^+$. For CTAB-kaolin, Cu(II) ions are mainly adsorbed via electrostatic attraction with the counter ions in the electric double layer ($Br^-$), via ion pairing, Cu(II) ions removal by the activated carbon is probably related to the carbon-oxygen groups particularly those of acid type. The adsorption capacities of CTAB-kaolin for the investigated adsorbates are considerably higher compared with those of unmodified kaolin. However, the adsorption capacities of the activated carbons are by far higher than those determined for CTAB-kaolin.

• Journal of the Korean institute of surface engineering
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• v.47 no.2
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• pp.68-74
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• 2014

The seed step-coverage enhancement process (SSEP) using Pd/Cu/PVP colloids was investigated for the filling of through silicon via (TSV) without void. TEM analysis showed that the Pd/Cu nano-particles were well dispersed in aqueous solution with the average diameter of 6.18 nm. This Pd/Cu nano-particles were uniformly deposited on the substrate of Si/$SiO_2$/Ti wafer using electrophoresis with the high frequency Alternating Current (AC). After electroless Cu deposition on the substrate treated with Pd/Cu/PVP colloids, the adhesive property between deposited Cu layer and substrate was evaluated. The Cu deposit obtained by SSEP with Pd/Cu/PVP colloids showed superior adhesion property to that on Pd ion catalyst-treated substrate. Finally, by implementing the SSEP using Pd/Cu/PVP colloids, we achieved 700% improvement of step coverage of Cu seed layer compared to PVD process, resulting in void-free filling in high aspect ratio TSV.