• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.1-6
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• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• Proceedings of the Korean Magnestics Society Conference
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• 2003.12a
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• pp.311-311
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• 2003

• Journal of Magnetics
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• v.21 no.2
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• pp.239-243
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• 2016

High temperature superconductor (HTS) magnet systems usually employ metal current leads which bridge between the cryogenic environment and room temperature. Such current leads are the dominant heat load for these magnet systems due to a combination of electrical resistance and heat conduction. HTS flux pumps enable large currents to be injected into a HTS magnet circuit without this heat load. We present results from an axial-type HTS mechanically rotating flux pump which employs a ferromagnetic circuit and a Cu-stabilized coated conductor (CC) HTS stator. We show the device can be described by a simple circuit model which was previously used to describe barrel-type flux pumps, where the model comprises an internal resistance due to dynamic resistance and a DC voltage source. Unlike previously reported devices, we show the internal resistance and DC voltage in the flux pump are not exactly proportional to frequency, and we ascribe this to the presence of eddy currents. We also show that this axial-type flux pump has superior current injection capability over barrel-type flux pumps which do not incorporate a magnetic circuit.

• Korean Journal of Materials Research
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• v.26 no.11
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• pp.604-610
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• 2016

We report on the fabrication and characterization of a novel $Cu_2O/CuO$ heterojunction structure with CuO nanorods embedded in $Cu_2O$ thin film as an efficient photocathode for photoelectrochemical (PEC) solar water splitting. A CuO nanorod array was first prepared on an indium-tin-oxide-coated glass substrate via a seed-mediated hydrothermal synthesis method; then, a $Cu_2O$ thin film was electrodeposited onto the CuO nanorod array to form an oxide semiconductor heterostructure. The crystalline phases and morphologies of the heterojunction materials were examined using X-ray diffraction and scanning electron microscopy, as well as Raman scattering. The PEC properties of the fabricated $Cu_2O/CuO$ heterojunction photocathode were evaluated by photocurrent conversion efficiency measurements under white light illumination. From the observed PEC current density versus voltage (J-V) behavior, the $Cu_2O/CuO$ photocathode was found to exhibit negligible dark current and high photocurrent density, e.g. $-1.05mA/cm^2$ at -0.6 V vs. $Hg/HgCl_2$ in $1mM\;Na_2SO_4$ electrolyte, revealing the effective operation of the oxide heterostructure. The photocurrent conversion efficiency of the $Cu_2O/CuO$ photocathode was estimated to be 1.27% at -0.6 V vs. $Hg/HgCl_2$. Moreover, the PEC current density versus time (J-T) profile measured at -0.5 V vs. $Hg/HgCl_2$ on the $Cu_2O/CuO$ photocathode indicated a 3-fold increase in the photocurrent density compared to that of a simple $Cu_2O$ thin film photocathode. The improved PEC performance was attributed to a certain synergistic effect of the bilayer heterostructure on the light absorption and electron-hole recombination processes.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.10
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• pp.889-894
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• 2007

We investigated the quench velocity of superconducting fault current limiter (SFCL) dependent on the source voltage. $YBa_2Cu_3O_7$ (YBCO) thin film was used as the current limiting element for SFCL. The analysis on the quench velocity of SFCL is essential to determine the capacity of circuit breaker (CB) or coordinate with CB. Generally, the quench velocity of SFCL is related with the short-circuit current. To change the short-circuit current, in this paper, the amplitude of the power source voltage is adjusted. Through the fault current limiting experiments, the quench velocity of SFCL was confirmed to increase fast as the source voltage increased. On the other hand, the peak limited current was shown to increase with steady rate of increase.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.61-67
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• 2020

In this paper, we calculated the warpage of bare substrates and chip attached substrates by using FEM (Finite Element Method), and compared and analyzed the effect of the chips' attachment on warpage. Also, the effects of layer thickness of substrates for reducing warpage were analyzed and the conditions of layer thickness were analyzed by signal-to-noise ratio of Taguchi method. According to the analysis results, the direction of warpage pattern in substrates can change when chips are attached. Also, the warpage decreases as the difference in the CTE (coefficient of thermal expansion) between the top and bottom of the package decreases and the stiffness of the package increases after chips are loaded. In addition, according to the impact analysis of design parameters on substrates where chips are not attached, in order to reduce warpage, the inner layers of the circuit layer Cu1 and Cu4 has be controlled first, and then concentrated on the thickness of the solder resist on the bottom side and the thickness of the prepreg layer between Cu1 and Cu2.

• Current Applied Physics
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• v.18 no.12
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• pp.1571-1576
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• 2018

Recent study shows that the main reason for limiting CZTS device performance lies in the low open circuit voltage, and crucial factor that could affect the $V_{oc}$ is secondary phases like ZnS existing in absorber layer and its interfaces. In this work, the $Cu_2ZnSnS_4$ thin film solar cells were prepared by sputtering CuSn and CuZn alloy targets. Through tuning the Zn/Sn ratios of the CZTS thin films, the crystal structure, morphology, chemical composition and phase purity of CZTS thin films were characterized by X-Ray Diffraction (XRD), scanning electron microscopy (SEM) equipped with an energy dispersive spectrometer (EDS) and Raman spectroscopy. The statistics data show that the CZTS solar cell with a ratio of Zn/Sn = 1.2 have the best power convention efficiency of 5.07%. After HCl etching process, the CZTS thin film solar cell with the highest efficiency 5.41% was obtained, which demonstrated that CZTS film solar cells with high efficiency could be developed by sputtering CuSn and CuZn alloy targets.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.298-302
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• 2010

We investigated the resistance change behavior of SABiT (Samsung Advanced Bump interconnection Technology) technology-applied PCB (Printed Circuit Board) with the various bump sizes and fabrication conditions. Many testing samples with different bump size, prepreg thickness, number of print on the formation of Ag paste bump, were made. The resistance of Ag paste bump itself was calculated from the Ag paste resistivity and bump size, measured by using 4-point probe method and FE-SEM (Field Emission Scanning Electron Microscope), respectively. The contact resistance between Ag paste bump and conducting Cu line were obtained by subtracting the Cu line and bump resistances from the measured total resistance. It was found that the contact resistance drastically changed with the variation of Ag paste bump size and the contact resistance had the largest influence on total resistance. We found that the bump size and contact resistance obeyed the power law relationship. The resistance of a circuit in PCB can be estimated from this kind of relationship as the bump size and fabrication technique vary.

• Membrane Journal
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• v.13 no.1
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• pp.9-19
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• 2003

Membrane process was investigated to recover process water and valuable gold from washing water of electroless PCB plating processes. The filtration experiments were carried out using not only a RO membrane test cell to determine suitable membrane for washing water but also spiral wound membrane modules of nanofiltration and reverse osmosis for scale-up. At first, RO-TL(tap water, low pressure), RO-BL(brackish water, low pressure) and RO-normal(for water purifier) sheet membranes made by Saehan Co. were tested, and the performance of RO-TL membrane showed most suitable f3r recovery of soft etching, catalyst and Ni washing waters. As a result of RO test cell, the experiments for scale-up were carried out using RO-TL modules far water purifier at 7bar and $25^{\circ}C $The permeate flux fur Au washing water was about 30 LMH, but Au rejection was less than 80%. The permeate fluxes for Pd, Ni and soft etching washing water were about 22, 17 and 10 LMH, respectively. The Pd, Ni and Cu rejections showed more than 85, 97 and 98% respectively. The nanofiltration module for water purifier was introduced to recover Au selectively from Au, Ni and Cu ions in Au washing water. Most of Ni and Cu ions in the feed washing water were removed, and only Au ion was existed 81.9% in the permeate. Furthermore, Au ion in the permeate was concentrated and recovered by RO-TL membrane module. Finally, Au was also able to recover effectively by using 4 inch diameter spiral wound modules of NF and RO-TL membranes, in series.