• ETRI Journal
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• v.33 no.4
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• pp.656-659
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• 2011

In ICISC 2007, Comuta and others showed that among the methods for constructing pairing-friendly curves, those using cyclotomic polynomials, that is, the Brezing-Weng method and the Freeman-Scott-Teske method, are affected by Cheon's algorithm. This paper proposes a method for searching parameters of pairing-friendly elliptic curves that induces minimal security loss by Cheon's algorithm. We also provide a sample set of parameters of BN-curves, FST-curves, and KSS-curves for pairing-based cryptography.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1510-1516
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• 2011

As emergence of the ubiquitous society, it is possible to access the network for services needed to us in anytime and anywhere. The phenomena has been accelerated by revitalization of the sensor network offering the sensing information and data. Currently, sensor network contributes the convenience for various services such as environment monitoring, health care and home automation. However, sensor network has a weak point compared to traditional network, which is easily exposed to attacker. For this reason, messages communicated over the sensor network, are encrypted with symmetric key and transmitted. A number of symmetric cryptography algorithms have been researched. Among of them HIGHT algorithm in hardware and software implementation are more efficient than tradition AES in terms of speed and chip size. Therefore, it is suitable to resource constrained devices including RFID tag, Sensor node and Smart card. In the paper, we present the optimized software implementation on the ultra-light symmetric cryptography algorithm, HIGHT.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.4
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• pp.548-555
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• 2022

This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.

• The KIPS Transactions:PartC
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• v.11C no.5
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• pp.569-576
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• 2004

Conventional researches of standard tool validating public key cryptographic algorithm have been studied for the internet environment, not for the mobile internet. It is important to develop the validation tool for establishment of interoperability and convenience of users in mobile internet. Therefore, this paper presents the validation tool of Elliptic Curie Cryptography algorithm that can test if following X9.62 technology standard specification. The validation tool can be applied all information securities using ECDSA, ECKCDSA, ECDH, etc. Moreover, we can en-hace the precision of validation through several experiments and perform the validation tool in the online environment.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.502-510
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• 2009

Multiprecision squaring is one of the most significant algorithms in the core public key cryptography operation. The aim of this work is to present a new improved squaring algorithm compared with the MIRACL's multi precision squaring algorithm in which the previous work [1] on multiprecision multiplication is implemented. First, previous works on multiprecision multiplication and standard squaring are analyzed. Then, our new Lazy Doubling squaring algorithm is introduced. In MIRACLE library [3], Scott's Carry-Catcher Hybrid multiplication technique [1] is applied to implementation of multiprecision multiplication and squaring. Experimental results of the Carry-Catcher hybrid squaring algorithm and the proposed Lazy Doubling squaring algorithm both of which are tested on Atmega128 CPU show that proposed idea has achieved significant performance improvements. The proposed Lazy Doubling Squaring algorithm reduces addition instructions by the fact $a_0\;{\ast}\;2\;+\;a_1\;{\ast}\;2\;+\;...\;+\;a_{n-1}\;{\ast}\;2\;+\;a_n\;{\ast}\;2\;=\;(a_0\;+\;a_1\;+\;...\;+\;a_{n-1}\;+\;a_n)\;{\ast}\;2$ while the standard squaring algorithm reduces multiplication instructions by the fact $S_{ij}\;=\;x_i\;{\ast}\;x_j\;=\;S_{ij}$. Experimental results show that the proposed squaring method is 25% faster than that in MIRACL.

• Journal of IKEEE
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• v.24 no.4
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• pp.961-968
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• 2020

This paper describes a design of high performance modular multiplier that is essentially used for elliptic curve cryptography. Our modular multiplier supports modular multiplications for five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2, and it calculates modular multiplication in two steps with integer multiplication and reduction. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. The division operation is performed only once for a given modulo value, and it was designed to skip division operation when continuous modular multiplications with the same modulo value are calculated. It was estimated that our modular multiplier can perform 6.4 million modular multiplications per second when operating at a clock frequency of 32 MHz. It occupied 456,400 gate equivalents (GEs), and the estimated clock frequency was 67 MHz when synthesized with a 180-nm CMOS cell library.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.2
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• pp.795-800
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• 2012

Recently, as communication is evolved by leaps and bounds through wired/wireless networks, variety of services are routinely made through communication networks. Accordingly, technology that is for protecting data and personal information is required essentially, and study of security technology is actively being make progress to solve these information protection problems. In this paper, to expand selection scope of the key of elliptic curve cryptography, arithmetic items of real number based elliptic curve algorithm among various cryptographic algorithms was studied. The result of an experiment, we could know that elliptic curve cryptography using the real number can choose more various keys than existing elliptic curve cryptography using integer and implement securer cryptographic system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2322-2326
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• 2011

General cryptosystem uses differently the data and key value for the increment of security level, processes the repetition of limited number and increases the periodic feature of LFSR similar infinite series. So, it cause the efficiency of the cryptosystem. In this thesis, proposed algorithm is composed of reformat, permutation, data cipher block and key scheduler which is applied the new function by mixed symmetric cryptography and asymmetric cryptography. We design the cryptosystem of smart card using the common Synopsys and simulate by ALTERA MAX+PLUS II at 40MHz. Consequently, we confirm the 52% increment of processing rate and the security level of 16 rounds.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.5
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• pp.2680-2700
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• 2017

Finite field arithmetic over GF($2^m$) is used in a variety of applications such as cryptography, coding theory, computer algebra. It is mainly used in various cryptographic algorithms such as the Elliptic Curve Cryptography (ECC), Advanced Encryption Standard (AES), Twofish etc. The multiplication in a finite field is considered as highly complex and resource consuming operation in such applications. Many algorithms and architectures are proposed in the literature to obtain efficient multiplication operation in both hardware and software. In this paper, a modified serial multiplication algorithm with interleaved modular reduction is proposed, which allows for an efficient realization of a sequential polynomial basis multiplier. The proposed sequential multiplier supports multiplication of any two arbitrary finite field elements over GF($2^m$) for generic irreducible polynomials, therefore made versatile. Estimation of area and time complexities of the proposed sequential multiplier is performed and comparison with existing sequential multipliers is presented. The proposed sequential multiplier achieves 50% reduction in area-delay product over the best of existing sequential multipliers for m = 163, indicating an efficient design in terms of both area and delay. The Application Specific Integrated Circuit (ASIC) and the Field Programmable Gate Array (FPGA) implementation results indicate a significantly less power-delay and area-delay products of the proposed sequential multiplier over existing multipliers.