• Review of KIISC
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• v.10 no.2
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• pp.11-20
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• 2000

WAP forum에서 제안한 WAP은 무선 인터넷을 위해 전세계적으로 가장 많이 사용되는 규격으로 무선 환경의 제약성을 고려하여 설계되었다 WAP은 다양한 응용 서비스의 보안을 위해 WTLS, WMLScript Crypto Library, WIM 그리고 WPKI에 대한 규격을 포함하지만 게이트웨이 모델을 사용함에 따른 구조적인 보안 결함을 가진다. 본 논문에서는 WAP보안을 위한 구성 요소들에 대해 검토하고 현재 WAP 보안의 문제점에 대해 논의한 후 그것을 해결하기 위한 WAP forum 의 보안 표준화 방향에 대해 고찰하고자 한다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.34-37
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• 2004

인터넷을 기반으로 하는 금융서비스를 제공함에 있어 보안성에 대한 필요성이 최근 들어 매우 중요시되어져가고 있으며, 이 분야에 대한 많은 연구가 진행되어 오고 있다. 국내 대부분의 은행 기관에서는 인터넷 뱅킹 서비스를 지원하고 있으나, 그 서비스 이용에 있어 윈도우 사용자에 국한되어 있는 실정이다. 본 논문에서는 리눅스 기반에서 보다 더 안전한 인터넷 뱅킹 서비스를 지원하기 위한 PKI 기반 기술을 제안한다.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.232-236
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• 2001

본 논문에서는 WAP 포럼에서 제시하고 있는 무선 인터넷 솔루션인 WAP에서의 보안 메커니즘인 WTLS(Wireless Transport Layer Security), WIM (WAP Identity Module), WMLScript Crypto Library, WPKI(WAP Public Key Infrastructure)에 대해 살펴보고, WAP 게이트웨이를 사용하는 네트워크의 구조적 형태에서 발생되는 종단간 보안 서비스의 문제점에 대해 논의한 후 WAP 환경에서 종단간 보안 서비스를 제공할 수 있는 보안 시스템을 설계 및 구현하고자 한다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5A
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• pp.554-565
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• 2004

In this paper, we implement single cycle and multi cycle adders. We can compare area and time by using the implemented adders. The size of adders is 64, 128, 256-bits. The architecture of hybrid adders is that the carry-out of small adder groups can be interconnected by utilizing n carry propagate unit. The size of small adder groups is selected in three formats - 4, 8, 16-bits. These adders were implemented with Verilog HDL with top-down methodology, and they were verified by behavioral model. The verified models were synthesized with a Samsung 0,35(um), 3.3(V) CMOS standard cell library while a using Synopsys Design Compiler. All adders were synthesized with group or ungroup. The optimized adder for a Crypto-processor included Smart Card IC is that a 64-bit RCA based on 16-bit CLA. All small adder groups in this optimized adder were synthesized with group. This adder can operate at a clock speed of 198 MHz and has about 961 gates. All adders can execute operations in this won case conditions of 2.7 V, 85 $^{\circ}C$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.6
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• pp.29-39
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• 2007

RSA is one of the most popular public-key crypto-system in various applications. This paper addresses a high-speed RSA crypto-processor with modified radix-4 modular multiplication algorithm and Chinese Remainder Theorem(CRT) using Carry Save Adder(CSA). Our design takes 0.84M clock cycles for a 1024-bit modular exponentiation and 0.25M cycles for a 512-bit exponentiations. With 0.18um standard cell library, the processor achieves 365Kbps for a 1024-bit exponentiation and 1,233Kbps for two 512-bit exponentiations at a 300MHz clock rate.

• Annual Conference of KIPS
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• 2000.04a
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• pp.447-464
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• 2000

많은 사람들이 관심을 가지고 급속도로 발전하는 인터넷 환경의 웹 서비스 중에서 인터넷 뱅킹 시스템은 반드시 필요한 서비스 중의 하나지만, 아직까지 많은 보안상의 문제점을 내포하고 있다. 본 논문에서는 이런 보안상의 문제들 중에서 사용자 인증에 관한 부분, 데이터 암호화에 관한 부분, 키 분배 문제에 관한 부분을 해결할 수 있는 방안을 제시하려 한다. 이를 위해 공개적으로 사용이 가능한 암호 라이브러리인 Crypto++3.1을 이용하여 인터넷 환경에서 보안 서비스를 제공할 수 있는 안전한 인터넷 뱅킹 시스템인 SIBS(Secure Internet Banking System)을 설계 및 구현하였다. SIBS는 빠른 데이터 암호화 처리를 위해 IDEA암호 알고리즘을 사용하였다. 데이터 암호화에 사용할 키를 분배하기 위해서 Diffie-Hellaman키 분배 알고리즘을 이용한다. 또한, 사용자의 인증을 위해 X.509형식의 인증서를 이용하기 위해서 SSLeay를 설치하여 인증서(Certificate)를 발급 받는다. 그러므로, 사용자는 인터넷에서 SIBS의 GUI(Graphic User Interface)를 이용해 빠르고 편리한 접근이 용이하고, 암호 알고리즘에 대한 지식이나 특별한 조치가 없이도 빠른 데이터 암호화 처리와 인증서를 이용한 확실한 사용자 인증을 보장 받을 수 있다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1296-1302
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT that was specified as a block cipher standard for lightweight cryptography ISO/IEC 29192-2 is described in this paper. Two types of crypto-core that support master key size of 80-bit are designed, one is for encryption-only function, and the other is for encryption and decryption functions. The designed PR80 crypto-cores implement the basic cipher mode of operation ECB (electronic code book), and it can process consecutive blocks of plaintext/ciphertext without reloading master key. The PR80 crypto-cores were designed in soft IP with Verilog HDL, and they were verified using Virtex5 FPGA device. The synthesis results using $0.18{\mu}m$ CMOS cell library show that the encryption-only core has 2,990 GE and the encryption/decryption core has 3,687 GE, so they are very suitable for IoT security applications requiring small gate count. The estimated maximum clock frequency is 500 MHz for the encryption-only core and 444 MHz for the encryption/decryption core.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.