• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.75-75
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• 2015

Strong interactions between electromagnetic radiation and electrons at metallic interfaces or in metallic nanostructures lead to resonant oscillations called surface plasmon resonance with fascinating properties: light confinement in subwavelength dimensions and enhancement of optical near fields, just to name a few [1,2]. By utilizing the properties enabled by geometry dependent localization of surface plasmons, metal photonics or plasmonics offers a promise of enabling novel photonic components and systems for integrated photonics or sensing applications [3-5]. The versatility of the nanoplasmonic platform is described in this talk on three folds: our findings on an enhanced ultracompact photodetector based on nanoridge plasmonics for photonic integrated circuit applications [3], a colorimetric sensing of miRNA based on a nanoplasmonic core-satellite assembly for label-free and on-chip sensing applications [4], and a controlled fabrication of plasmonic nanostructures on a flexible substrate based on a transfer printing process for ultra-sensitive and noise free flexible bio-sensing applications [5]. For integrated photonics, nanoplasmonics offers interesting opportunities providing the material and dimensional compatibility with ultra-small silicon electronics and the integrative functionality using hybrid photonic and electronic nanostructures. For sensing applications, remarkable changes in scattering colors stemming from a plasmonic coupling effect of gold nanoplasmonic particles have been utilized to demonstrate a detection of microRNAs at the femtomolar level with selectivity. As top-down or bottom-up fabrication of such nanoscale structures is limited to more conventional substrates, we have approached the controlled fabrication of highly ordered nanostructures using a transfer printing of pre-functionalized nanodisks on flexible substrates for more enabling applications of nanoplasmonics.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2014년도 하계학술대회
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• pp.163-165
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• 2014

In this paper, we propose a world's first programmable video processing platform for video quality enhancement of 8K ($7680{\times}4320$) UHD (Ultra High Definition) TV at 60 frames per second. To support huge computation and memory bandwidth of video quality enhancement for 8K resolution, the proposed platform has unique features like symmetric multi-cluster architecture for data partitioning, ring data-path between clusters to support data pipelining, on-the-fly processing architecture to reduce DDR bandwidth, flexible hardware to accelerating common kernel in video enhancement algorithms. In addition to those features, general programmability of SRP (Samsung reconfigurable processor) as main core of the proposed platform makes it possible to upgrade continuously video enhancement algorithm even after the platform is fixed. This ability is very important because algorithms for 8K DTV is under development. The proposed sub-system has been embedded into SoC (System on Chip) and new 8K UHD TV using the programmable SoC is expected at CES2015 for the first time in the world.

• 한국정보통신학회논문지
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• 제10권10호
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• pp.1804-1809
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• 2006

본 고에서는 디지털 회로의 저 전력소모의 설계와 구현에 관련된 디지털 전대역 회로 설계를 통해서 전반적인 전력 소모의 방법론과 이의 특성을 고찰하고자 한다. 디지털 집적회로의 설계는 광대하고 복잡한 영역이기에 우리는 이를 저전력 소모의 전반적인 회로 설계에 한정할 필요가 있다. 여기에는 로직회로의 합성과, 디지털 전대역 회로설계에 포함되어 있는 입력 clock 버퍼, 레치, 전압 Regulator, 그리고 케페시턴스와 전압기가 0.12 마이크론의 기술로 0.9V의 전압과 함께 쓰여져서 동적 그리고 정적 에너지 소모와 압력, 가속, Junction temperature 등을 모니터 할 수 있게 되어 있다.

• 마이크로전자및패키징학회지
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• 제20권2호
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• pp.33-38
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• 2013

In this study, both a finite element analysis and an experimental analysis are executed to investigate the mechanical characteristics of dielectric material effects on warpage. Also, viscoelastic material properties are measured by DMA and are considered in warpage simulation. A finite element analysis is done by using both thermal elastic analysis and a thermo-viscoelastic analysis to predict the nonlinear effects. For experimental study, specimens warpage of non-symmetric structure with body size of $22.5{\times}22.5$ mm, $37.5{\times}37.5$ mm and $42.5{\times}42.5$ mm are measured under the reflow temperature condition. From the analysis results, experimental warpage is not similar to FEA results using thermal elastic analysis but similar to FEA results using thermo-viscoelastic analysis. Also, its effect on substrate warpage is increased as core thickness is decreased and body size is getting larger. These FEA and the experimental results show that the nonlinear characteristics of dielectric material play an important role on substrate warpage. Therefore, it is strongly recommended that non-linear behavior characteristics of a dielectric material should be considered to control warpage of FCBGA substrate under conditions of geometry, structure and manufacturing process and so on.

• 전자공학회논문지SC
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• 제49권3호
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• pp.69-74
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• 2012

본 논문에서는 국방기술을 활용하여 전투병사의 귀를 폭음으로부터 보호하면서도 상호 교신의 어려움을 최소화하는 야전형 디지털 보청기에 관해 연구한 결과를 보여준다. 보청기는 작은 소리를 증폭하기도 하지만 급격하게 커지는 폭음은 오히려 감쇠시킬 수 있는 신호의 압축이 보편화되어 있다. 이를 전투 병사의 귀에 활용하면 그들의 귀를 보호하게 된다. 디지털 보청기의 개발 과정은 핵심 부품인 DSP IC 칩이 개선되어 새로이 출시되면, 그에 대응해서 새로운 칩에 맞는 펌웨어와 휘팅 소프트웨어를 개발하면 된다. 최근에 캐나다 DSP Factory에서 설계 출시된 Ezairo 5910칩을 가지고 현재 연구되는 보청기 펌웨어 개발의 일부를 소개하고자 한다.

• 전자공학회논문지C
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• 제35C권12호
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• pp.31-39
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• 1998

본 논문은 휴대 멀티미디어 응용을 위한 고정 소수점 DSP(Multimedia Fixed-point DSP : MDSP) 칩 설계 및 구현에 관해 기술한다. MDSP는 멀티미디어 처리에 효율적인 명령어 집합을 가지며 SIMD, 벡터프로세싱의 병렬처리 기술과 DSP 기술의 장점을 접목하여 설계되었다. MDSP는 한 개의 데이터 경로가 목적에 따라 여러 개로 분할될 때 8, 16, 32, 40 비트 등의 다양한 데이터 형태의 처리가 가능하며, 멀티미디어 응용영역에서 핵심적인 역할을 하는 MAC 연산을 한 사이클에 2개를 수행하여 성능을 향상시킨다. 새롭게 제안된 스위칭 네트워크와 Packing 네트워크는 MPEG 디코딩, 인코딩, 콘볼루션 등의 알고리즘 처리시 연산과 데이터 변환을 중첩시켜 성능을 향상시킨다. Verilog HDL 모델을 구현하였고 0.6 ㎛ SOG 라이브러리(KG75000)를 이용하여 논리합성 및 시뮬레이션 하였다. 전체 게이트 수는 68,831개이며 MDSP는 30MHz에 동작한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.473-481
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• 2013

A fractional folding analog-to-digital converter (ADC) with a novel arithmetic digital encoding technique is discussed. In order to reduce the asymmetry errors of the boundary conditions for the conventional folding ADC, a structure using an odd number of folding blocks and fractional folding rate is proposed. To implement the fractional technique, a new arithmetic digital encoding technique composed of a memory and an adder is described. Further, the coding errors generated by device mismatching and other external factors are minimized, since an iterating offset self-calibration technique is adopted with a digital error correction logic. A prototype 8-bit 1GS/s ADC has been fabricated using an 1.2V 0.13 um 1-poly 6-metal CMOS process. The effective chip area is $2.1mm^2$(ADC core : $1.4mm^2$, calibration engine : $0.7mm^2$), and the power consumption is 88 mW. The measured SNDR is 46.22 dB at the conversion rate of 1 GS/s. Both values of INL and DNL are within 1 LSB.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권4호
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• pp.211-216
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• 2003

This work describes a 3 V 12b 100 MS/s CMOS digital-to-analog converter (DAC) for high-speed communication system applications. The proposed DAC is composed of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs, trading-off linearity, power consumption, chip area, and glitch energy with this process. The low-glitch switch driving circuits are employed to improve linearity and dynamic performance. Current sources of the DAC are laid out separately from the current-cell switch matrix core block to reduce transient noise coupling. The prototype DAC is implemented in a 0.35 um n-well single-poly quad-metal CMOS technology and the measured DNL and INL are within ${\pm}0.75$ LSB and ${\pm}1.73$ LSB at 12b, respectively. The spurious-free dynamic range (SFDR) is 64 dB at 100 MS/s with a 10 MHz input sinewave. The DAC dissipates 91 mW at 3 V and occupies the active die area of $2.2{\;}mm{\;}{\times}{\;}2.0{\;}mm$

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1996년도 추계학술발표회논문집(1)
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• pp.191-196
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• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 기술심포지움 논문집
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)