• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.56-61
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• 2018

In this paper, a new type of active snubber was proposed to lower the excessive rated voltage of the clamp capacitor which was a problem in the conventional circuit by applying auxiliary winding into the active snubber. A simplified equivalent circuit of the proposed snubber was derived by applying it to QR flyback converter, and the equivalent circuits for each switch state was shown under the steady-state condition. In addition, the maximum voltage of the clamp capacitor as well as the main switch was found by using the steady-state equations. In particular, it was found that the clamp capacitor voltage could be controlled by the auxiliary winding ratio. In order to verify the utility and practicality of the proposed converter with auxiliary winding type active snubber circuit, a prototype with an output voltage of 19V and a maximum load current of 6A was produced and the results were reported.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.256-260
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• 2001

This paper presents boost and buck and buck-boost DC-DC converter circuit topologies of high-frequency soft switching transition PWM chopper type DC-DC high power converters with a single auxiliary passive resonant snubber. In the proposed boost power converter circuits operating under a principle of ZCS turn-on and ZVS turn-off commutation schemes, the capacitor and inductor in the auxiliary passive resonant circuit works as the loss less resonant snubber. In addition to this, the switching voltage and current peak stresses as well as EMI and RFI noises can be basically reduced by this single passive resonant snubber. Moreover, it is proved that converter circuit topologies with a passive resonant snubber are capable of solving some problems of the conventional hard switching PWM processing based on high-ferquency pulse modulation operation principle. The simulation results of this converter are discussed as compared with the experimental ones. The effectiveness of this power converter with a single passive resonant snubber is verified by the 5kW experimental breadboad set up.

• Journal of Power Electronics
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• v.14 no.5
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• pp.882-889
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• 2014

This paper presents a zero voltage switching (ZVS) converter with three resonant tanks. The main advantages of the proposed converter are its ability to reduce the switching losses on the power semiconductors, decrease the current stress of the passive components at the primary side, and reduce the transformer secondary windings. Three resonant converters with the same power switches are adopted at the low voltage side to reduce the current rating on the transformer windings. Using a series-connection of the transformer secondary windings, the primary side currents of the three resonant circuits are balanced to share the load power. As a result, the size of both the transformer core and the bobbin are reduced. Based on the circuit characteristics of the resonant converter, the power switches are turned on at ZVS. The rectifier diodes can be turned off at zero current switching (ZCS) if the switching frequency is less than the series resonant frequency. Therefore, the reverse recovery losses on the rectifier diodes are overcome. Experiments with a 1.6kW prototype are presented to verify the effectiveness of the proposed converter.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2212-2220
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• 2016

Based on the conventional PID algorithm and the adaptive PID (AD-PID) algorithm, a separate sampling adaptive PID (SSA-PID) algorithm is proposed to improve the transient response of digitally controlled DC-DC converters. The SSA-PID algorithm, which can be divided into an oversampled adaptive P (AD-P) control and an adaptive ID (AD-ID) control, adopts a higher sampling frequency for AD-P control and a conventional sampling frequency for AD-ID control. In addition, it can also adaptively adjust the PID parameters (i.e. $K_p$, $K_i$ and $K_d$) based on the system state. Simulation results show that the proposed algorithm has better line transient and load transient responses than the conventional PID and AD-PID algorithms. Compared with the conventional PID and AD-PID algorithms, the experimental results based on a FPGA indicate that the recovery time of the SSA-PID algorithm is reduced by 80% and 67% separately, and that overshoot is decreased by 33% and 12% for a 700mA load step. Moreover, the SSA-PID algorithm can achieve zero overshoot during startup.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.161-161
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• 2010

In order to achieve low power consumption and the uniform power spectrum of LED BLU (Back Light Unit) system, new circuits with a 2 stage L-C (Inductor-Capacitor) coupler have been proposed. From the simulation results based on our proposed model, the ripple power of the L-C regulation-embedded BLU circuit shows a dramatic reduction by more than 89.3% as compared to the normal BLU (without L-C circuits). This indicates that the proposed circuit is very promising for the realization of high-efficiency BLU circuits.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.93-96
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• 2001

A design methodology of analog circuits for a CMOS stereo 16-bit Δ$\Sigma$ DAC which are suitable for the digital audio applications is described. The limitations of Δ$\Sigma$ DAC exist in the performance of the 1-bit DAC and that of the smoothing filter. The proposed architecture for analog circuits contains the buffer between the digital modulator and the following analog stage and adopts the SCF (switched capacitor filter) and DSC (differential-to-single converter) scheme. In this paper, a guide line for the selection of the filter type for the SCF design in the Δ$\Sigma$ DAC is suggested through the analytical approaches.

• Progress in Superconductivity
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• v.9 no.2
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• pp.157-161
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• 2008

Due to high speed operations and ultra low power consumptions RSFQ logic circuit is a very good candidate for future electronic device. The focus of the RSFQ circuit development has been on the advancement of analog-to-digital converters and microprocessors. Recent works on RSFQ ALU development showed the successful operation of an 1-bit block of ALU at 40 GHz. Recently, the study of an RSFQ analog-to-digital converter has been extended to the development of a single chip RF digital receiver. Compared to the voltage logic circuits, RSFQ circuits operate based on the pulse logic. This naturally leads the circuit structure of RSFQ circuit to be pipelined. Delay time on each pipelined stage determines the ultimate operating speed of the circuit. In simulations, a two junction Josephson transmission line's delay time was about 10 ps, a splitter's 14.5 ps, a switch's 13 ps, a half adder's 67 ps. Optimization of the 4-bit ALU circuit has been made with delay time consideration to operate comfortably at 10 GHz or above.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.627-628
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• 2006

A low-voltage switched-capacitor $2^{nd}$-order $\Sigma\Delta$ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the $\Sigma\Delta$ loop. These features greatly relax the DC gain and output swing requirements for Op-Amp in the low-voltage $\Sigma\Delta$ modulator. Implemented by a 0.18-${\mu}m$ CMOS technology, the $\Sigma\Delta$ modulator satisfies performance requirements for WCDMA and CDMA2000 standards.

• Journal of Power Electronics
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• v.15 no.3
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• pp.587-601
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• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1634-1644
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• 2016

In this paper, a current-fed two-inductor bi-directional DC/DC converter using resonance (CF-TIBCR) and its design method are proposed. The CF-TIBCR has characteristics of low current ripple and a high current rating because of two separated inductors. Also, it achieves zero voltage switching for all switches and zero current switching for switches of a low voltage stage by using the resonant tank. Besides, a voltage spike problem in conventional current-fed converters is solved without the need for an additional snubber or clamping circuits. As a result, the CF-TIBCR features high step-up and high efficiency. Since the proposed converter has difficulty achieving the soft-switching condition when the converter requires the low voltage transfer ratio, a method that varies the number of resonant cycles is adopted to extend the output voltage range with satisfying the soft-switching condition. The principles of the operation characteristics are presented with a theoretical analysis, and the proposed converter is verified through results of an experiment using a laboratory prototype.