• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.2
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• pp.639-643
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• 2018

As electronic systems become smaller and more portable, the need for power conversion continues to increase. In addition, system stability must be ensured from switching noise due to power conversion efficiency and power conversion system miniaturization. Therefore, countermeasures to reduce switching noise during power conversion are essential. In this paper, a DC/DC buck converter circuit is constructed, and the characteristics of switching noise generated when changing the parts layout in a four-layer printed circuit board (PCB) structure with a reference plane are compared and analyzed. In addition, switching noise characteristics were compared and analyzed through simulations when the parts layout was different in a two-layer PCB structure from which the reference planes were removed. As a result, it was confirmed that the radiated emissions characteristic is reduced by 12dB and the conducted emissions characteristic decreased by 7dB to 8dB, according to the current return path in the four-layer PCB structure. Thus, it was confirmed that the noise characteristics can be improved according to the configuration of the current return path when the power conversion circuit is designed.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.311-312
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• 2010

The fabricated photovoltaic cells based on PIN heterojunctions, in this study, have a structure of ITO/poly(3, 4-ethylenedioxythiophene)-poly(styrenesulfonate)(PEDOT:PSS)/donor/donor:C60(10nm)/C60(35nm)/2, 9-dimethyl-4, 7-diphenyl-1, 10-phenanthroline(8nm)/Al(100nm). The thicknesses of an active layer(donor:C60), an electron transport layer(C60), and hole/exciton blocking layer(BCP) were fixed in the organic photovoltaic cells. We investigated the performance characteristics of the PIN organic photovoltaic cells with copper phthalocyanine(CuPc), tetracene and pentacene as a hole transport layer. Discussion on the photovoltaic cells with CuPc, tetracene and pentacene as a hole transport layer is focussed on the dependency of the power conversion efficiency on the deposition rate and thickness of hole transport layer. The device performance characteristics are elucidated from open-circuit-voltage(Voc), short-circuit-current(Jsc), fill factor(FF), and power conversion efficiency($\eta$). As the deposition rate of donor is reduced, the power conversion efficiency is enhanced by increased short-circuit-current(Jsc). The CuPc-based PIN photovoltaic cell has the limited dependency of power conversion efficiency on the thickness of hole transport layer because of relatively short exciton diffusion length. The photovoltaic cell using tetracene as a hole transport layer, which has relatively long diffusion length, has low efficiency. The maximum power conversion efficiencies of CuPc, tetracene, and pentacene-based photovoltaic cells with optimized deposition rate and thickness of hole transport layer have been achieved to 1.63%, 1.33% and 2.15%, respectively. The photovoltaic cell using pentacene as a hole transport layer showed the highest efficiency because of dramatically enhanced Jsc due to long diffusion length and strong thickness dependence.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10a
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• pp.255-258
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• 1996

This paper describes a DC voltage controller for the DC power supply which is constructed using the full-bridged MOS-FET DC-to-RF power inverter and rectifier. The full-bridged MOS-FET DC-to-RF inverter consisting of four MOSFET arrays and an output power transformer has a control function which is able to control the RF output power when the widths of the pulse voltages which are fed to four MOS-FET arrays of the fall-bridged inverter are changed using the pulse width control circuit. The power conversion efficiency of the full-bridged MOS-FET DC-to-RF power inverter was approximately 85 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The RF output voltage from the full-bridged MOS-FET DC-to-RF inverter is fed to the rectifier circuit through the output transformer. The rectifier circuit consists of GaAs schottky diodes and filters, each of which is made of a coil and capacitors. The power conversion efficiency of the rectifier circuit was over 80 % when the duty cycles of the pulse voltages were changed from 30 % to 50 %. The output voltage of the rectifier circuit was changed from 34.7V to 37.6 V when the duty cycles of the pulse voltages were changed from 30 % to 50 %.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.595-604
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• 2016

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

• Electrical & Electronic Materials
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• v.10 no.9
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• pp.930-937
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• 1997

Polycrystalline CdTe thin films have been studied for photovoltaic application because of their high absorption coefficient and optimal band energy(1.45 eV) for solar energy conversion. In this study CdTe thin films were deposited on CdS(chemical bath deposition)/ITO(indium tin oxide) substrate by rf-magnetron sputtering under various conditions. Structural optical and electrical properties are investigated with XRD UV-Visible spectrophotometer SEM and solar simulator respectively. The fabricated CdTe/CdS solar cell exhibited open circuit voltage( $V_{oc}$ ) of 610 mV short circuit current density( $J_{sc}$ ) of 17.2 mA/c $m^2$and conversion efficiency of about 5% at optimal sputtering conditions.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.20 no.7
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• pp.74-80
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• 2006

This paper describes a solar energy conversion strategy is applied to grid-connected single phase inverter by the maximum power point of conversion strategy. The maximum power point of tracking is controlled output power of PV(photovoltaic)modules, based on generated circuit control MOSFET switch of two boost converter for a connected single phase inverter with four IGBT's switch in full bridge. The generation control circuit allows each photovoltaic module to operate independently at peak capacity, simply by detecting of the output power of PV module. Furthermore, the generation control circuit attenuates low-frequency ripple voltage. which is caused by the full-bridge inverter, across the photovoltaic modules. The effectiveness of the proposed inverter system is confirmed experimentally and by means of simulation.

• Journal of the Institute of Convergence Signal Processing
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• v.1 no.2
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• pp.131-137
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• 2000

In this paper, as a compatible software radio transmission system, Digital-Radio conversion system which can directly change the digital signal generated by the logic circuit into radio signal is proposed. By the vector synthesis method, the digital signals can change directly into radio signal. If such a circuit is realized, RF circuit and an antenna can be composed by the simple one device, and the radio is directly controlled and performed by the software processing which is the essence of software radio. This Digital-Radio conversion system of this paper give many number of communication channels being offered by PN code and offer a hardware design flexibility by digitization, therefore it decrease the percentage ratio of hardware of system and give a more flexible function of software basis. In this paper, the principle of digital to radio signal generation algorithm is explained and the performance characteristics of proposed algorithm is shown in time base by the computer simulation method.

• Proceedings of the KIEE Conference
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• 1998.07f
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• pp.1869-1871
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• 1998

In this paper, we designed and fabricated a fast switching system for high power pulse. This system consists of a voltage conversion circuit, high voltage charging circuit, trigger circuit, and discharging circuit. Especially discharging line is designed by strip-line for low inductance and resistance. The experimental result is that current slew rate of the system is 6.67kA/86ns and this result is fully qualified for initiating EBW or EFI

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.5
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• pp.528-535
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• 1988

This paper presents a constructing theory of variable arithmetic operation systems for computing multiplications and multiplicative inverse in GF(2**m) based on a modulo operation of degree on elements in Galois fields. The proposed multiplier is composed of a zero element control part, input element conversion part, inversion circuit, and output element conversion part. These systems can reduce reasonable circuit areas due to the common use of input/output element converison parts, and the PLA and module structure provice a variable property capable of convertible uses as arithmetic operation systems over different finite fields. This type of designs gives simple, regular, expandable, and concurrent properties suitable for VLSI implementation. Expecially, the multiplicative inverse circuit proposed here is expected to offer a characteristics of the high operation speed than conventional method.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.545-548
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• 2004

The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.