• Nuclear Engineering and Technology
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• v.46 no.3
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• pp.381-386
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• 2014

A highly reliable safety class controller for NPPs (Nuclear Power Plants) is mandatory as even a minor malfunction can lead to disastrous consequences for people, the environment or the facility. In order to enhance the reliability of a safety class digital controller for NPPs, we employed a diversity approach, in which a PLC-type controller and a PLD-type controller are to be operated in parallel. We built and used structured testbenches based on the classes supported by UVM for functional verification of the PLD-type controller designed for NPPs. We incorporated a UVM register model into the testbenches in order to increase the controllability and the observability of the DUT(Device Under Test). With the increased testability, we could easily verify the datapaths between I/O ports and the register sets of the DUT, otherwise we had to perform black box tests for the datapaths, which is very cumbersome and time consuming. We were also able to perform constrained random verification very easily and systematically. From the study, we confirmed the various advantages of using the UVM register model in verification such as scalability, reusability and interoperability, and set some design guidelines for verification of the NPP controllers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.96-104
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• 2006

This paper presents design methodology, encient verification and implementation of a CAN protocol controller. The design methodology uses a heuristic technique to make the design flexible and cost effective. Using the design methodology, we created architecture for a CAN controller which has flexible and low cost features. For faster time-to-market and reliable operation of the designed CAN protocol controller, we p개posed a three-step verification process which uses three different kinds of verification techniques. The goal of this three-step verification is to reduce the number of test sequences in order to rapidly implement the design without loss of reliability for faster time-to-market. The designed CAN protocol controller was fabricated using a 0.35 micrometer CMOS technology.

• Journal of the Korea Society for Simulation
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• v.28 no.4
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• pp.11-20
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• 2019

This paper presents a HILS(Hardware-In-the-Loop Simulation) approach for the verification of the OHT (Overhead Hoist Transport) controller in a semiconductor FAB. Since hundreds of OHTs can run simultaneously on the OHT network of a FAB, the full verification of the OHT controller is very essential to guarantee the stableness of the material handling system. The controller needs to fully consider not only normal situations but also abnormal situations that are difficult to predict. For the verification of the controller, we propose a HILS approach using a virtual environment including OHTs on a rail network, which can generate abnormal situations. The proposed HILS approach has been implemented and tested with various examples.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.499-502
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• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• Nuclear Engineering and Technology
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• v.41 no.1
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• pp.79-90
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• 2009

Verification of programmable logic controller (PLC) programs written in IEC 61131-3 function block diagram (FBD) is essential in the transition from the use of traditional relay-based analog systems to PLC-based digital systems. This paper describes effective use of the well-known verification tool VIS for automatic verification of behavioral equivalences between successive FBD revisions. We formally defined FBD semantics as a state-transition system, developed semantic-preserving translation rules from FBD to Verilog programs, implemented a software tool to support the process, and conducted a case study on a subset of FBDs for APR-1400 reactor protection system design.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.312-314
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• 2006

This paper describes performance of the modified gain scheduling controller by speed control of a DC motor. The modified gain scheduling controller can perform tracking at more than one equilibrium points. The modified gain scheduling controller which considers transient response according to added zero shows better result of tracking performance than the unmodified gain scheduling controller shows.

• The KIPS Transactions:PartA
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• v.12A no.6 s.96
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• pp.523-530
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• 2005

When a PCI 2.2 bus master requests data using Memory Read command, a target device may hold PCI bus without data to be transferred for long time because a target device needs time to prepare data infernally. Because the usage efficiency of the PCI bus and the data transfer efficiency are decreased due to this situation, the PCI specification recommends to use the Delayed Transaction mechanism to improve the system performance. But the mechanism cann't fully improve performance because a target device doesn't know the exact size of prefetched data. In the previous work, we propose a new method called Prefetch Request when a bus master intends to read data from the target device. In this paper, we design PCI 2.2 controller and local device that support the proposed method. The designed PCI 2.2 controller has simple local interface and it is used to convert the PCI protocol into the local protocol. So the typical users, who don't know the PCI protocol, can easily design the PCI target device using the proposed PCI controller. We propose the basic behavioral verification, hardware design verification, and random test verification to verify the designed hardware. We also build the test bench and define assembler instructions. And we propose random testing environment, which consist of reference model, random generator ,and compare engine, to efficiently verify corner case. This verification environment is excellent to find error which is not detected by general test vector. Also, the simulation under the proposed test environment shows that the proposed method has the higher data transfer efficiency than the Delayed Transaction about $9\%$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.71-80
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• 2004

In this paper, we study for the design and verification of a 16 bits micro controller, which is compatible with a 8 bits micro controller, 8051, widely used in the industrial fields these days. To confirm our design, we verified our design for all instruction sets and various combinational sets of them. Also we propose a new idea for the verification of various instruction sets, We verified our design through some application programs such as IMA-ADPCM, SOLA. Finally, we verified our design for all instruction sets and application programs through an application board, used Xilinx FPGA(XCVl000-560C). After the comparison our design with a 8051 for various cases, We concluded that we could substitute our design for a 8051 and our design could be operated more powerfully than a 8051.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.39-49
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• 2006

This paper proposes an efficient verification environment of PCI Express controller that is the future I/O interface. This verification environment consists of a test vector generator, a test bench, and two abstract memories. We also define the assembler set to generate the verification scenarios. In this paper, we propose the random test environment which consists of a random vector generator, a .simulator part, and a compare engine. This verification methodology is useful to find the special errors which are not detected by the basic-behavioral test and hardware-design test.

• Korean Journal of Computational Design and Engineering
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• v.14 no.4
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• pp.225-233
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• 2009

The objective of this paper is to examine a construction method and verify PLC logic using the logical modeling and simulation of a virtual plant has complex manufacturing system and the domain of application is car body assembly line of automotive industrial operated by PLC Program. The proposed virtual plant model for the analysis of the construction method consists of three types of components which are virtual device, intermediary transfer and controller is modeled by logical model but it the case of the verification of PLC program, HMI and PLC logic in the field substitute for the controller. The implementation of the proposed virtual plant model is conducted PLC Studio which is an object-oriented modeling language based on logical model. As a result, proposed methods enable 3D graphics is designed in the analysis step to use for verification of PLC program without special efforts.