• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1535-1538
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• 2002

The flexibility of content addressable mem-ory (CAM) can greatly be extended through the use of trits (ternary digits) Trits consist of binary logical values “0” and “1” with addition of “x” (“dont’t care”). The “dont’t care“is extremely useful for providing com- pact representation of sets of bit strings. In this paper, we propose a new ternary CAM with Hamming distance search functions. Each memory cell in the CAM consists of a pair of lambda diodes which can store trits, namely, a logical “0”, “1” and “x” (“dont’t care“). The CAM can compare stored data and an input data in parallel, and find stored data with Hamming distance within a certain range (“near match“). Also, the interrogation characteristics of the ternary CAM are analyzed in detail. Furthermore, the results obtained these analyses are fully confirmed by simulation using the circuit analysis program HSPICE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1313-1323
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• 1991

n this thesis CAM(content Addressable Memory) generator and graphic display tool for run-plot sequence in automatic generation of CAM are presented. We show that implementing the layout generation, graphic menu, mouse driver, and data structure by using the basic classes is clear and easy in modification than the conventional procedural language. For the implementation of generator which is independent of design rule or process, we use the parameterized cell so that basic cell can be changed according to user's inputs. and perform the layout by means of placement and routing using pitch mathching. Finally, the display of CIF which generated and constitution of graphic menu for total run-plot sequence are explained.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.5
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• pp.587-592
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• 2004

Context-aware computing systems require real-time context reasoning process for context awareness. Context reasoning can be done by comparing input information from sensors with knowledge-base within system. This method is identical with it of rule-based systems. In this paper, we propose hardware rule-based system architecture which can process context reasoning in real-time. Compared to previous architecture, hardware rule-based system architecture can reduce the number of constraints on rule representations and combinations of condition terms in rules. The modified content addressable memory, crossbar switch network and pre-processing module are used for reducing constraints. Using SystemC for description can provide easy modification of system configuration later.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.7B
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• pp.647-659
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• 2003

LPM(Longest Prefix Matching)searching in If address lookup is a major bottleneck of IP packet processing in the high speed router. In the conventional lookup table for the LPM searching in CAM(Content Addressable Memory) the complexity of fast update take 0(1). In this paper, we designed pipeline architecture for fast update of 0(1) cycle of lookup table and high throughput and low area complexity on LPM searching. Lookup-table architecture was designed by CAM(Content Addressable Memory)away that uses 1bit RAM(Random Access Memory)cell. It has three pipeline stages. Its LPM searching rate is affected by both the number of key field blocks in stage 1 and stage 2, and distribution of matching Point. The RTL(Register Transistor Level) design is carried out using Verilog-HDL. The functional verification is thoroughly done at the gate level using 0.35${\mu}{\textrm}{m}$ CMOS SEC standard cell library.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.57-64
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• 2002

The structure of conventional CAM(Content Addressable Memory) cell, used to Look-up table scheme in Huffman CODEC, is not performed by being separated in reading, writing and match operation. So, there is disadvantages that the control is complicated, and the floating states of match line force wrong operation to be happened in reading, writing operation. In this paper, in order to improve the disadvantages and proces the data fast, fast Look-up table is designed using DBLCAM(Dual Bit Line CAM)-performing the reading, writing operation and match operation independently and Two-port SRAM being more fast than RAM in an access speed. Look-up table scheme in Huffman CODEC, using DBLCAM and Two-port SRAM proposed in this paper, is designed in Cadence tool, and layout is performed in 0.6${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS full custom. And simulation is peformed with Hspice.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.2
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• pp.39-46
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• 2012

The newly designed sense amplifier in this paper has rail-to-rail input range achieving low power consumption. Reducing static power consumption generated due to DC path to ground is key element for low power consumption in this paper. The proposed sense amplifier performs power-saving operation using negative feedback circuit that controls the current flow with the newly added PMOS input terminal. As a simulation result, the proposed sense amplifier consumed about over 50 % efficiency of the average power consumed by the typical Rail-to-Rail sense amplifier.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.769-776
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• 2023

In this paper, we designed an MLSA(Match-line Sense Amplifier) for low-power CAM(Content Addressable Memory). By using the MLSA and precharge controller, we reduced power consumption during CAM operation by employing a selective match-line charging technique to mitigate power consumption caused by mismatch. Additionally, we further reduced power consumption due to leakage current by terminating precharge early when a mismatch occurs during the search operation. The designed circuit exhibited superior performance compared to the existing circuits, with a reduction of 6.92% and 23.30% in power consumption and propagation delay time, respectively. Moreover, it demonstrated a significant decrease of 29.92% and 52.31% in product-delay-product (PDP) and energy-delay-product (EDP). The proposed circuit was validated using SPECTRE simulation with TSMC 65nm CMOS process.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.04a
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• pp.17-21
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• 2004

본 논문에서는 실시간으로 상수 및 변수의 병렬 매칭이 가능한 새로운 구조의 하드웨어 기반 룰-베이스시스템 구조를 제안한다. 이 시스템은 context-aware computing 시스템에서 상황 인식을 위한 기법으로 적용될 수 있다. 제안된 구조는 기존의 하드웨어 기반의 구조가 가지는 룰의 표현 및 룰의 구성에서 발생하는 제약을 상당히 감소시킬 수 있다. 이를 위해 변형된 형태의 content addressable memory(CAM)와 crossbar switch network(CSN)가 사용되었다. 변형된 형태의 CAM으로 구성된 지식-베이스는 동적으로 데이터의 추가 및 삭제가 가능하다. 또한 CSN은 input buffer와 working memory(WM) 사이에 위치하여, 시스템 외부 및 내부에서 동적으로 생성되거나, 시스템 설정에 의해 지정된 데이터들의 조합 및 pre-processing module(PPM)을 이용한 연산을 통하여 WM을 구성하는 데이터를 생성시킨다. 이 하드웨어 룰-베이스 시스템은 SystemC 2.0을 이용하여 설계하였으며 시뮬레이션을 통하여 그 동작을 검증하였다.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.205-208
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• 2002

An existing ATM switch fabric uses VPI(Virtual Path Identifier) and VCI(Virtual Channel Identifier) information to route ATM cell. But AAL type 2 switch which efficiently processes delay-sensitive, low bit-rate data such as a voice routes the ATM cell by using CID(Channel Identification) field in addition to VPI and VCI. In this paper, we research the AAL type 2 switch that performs the process of CPS packet. The Receive unit extracts the CPS packet from the inputted ATM cell. The designed receive unit consists of input FIFO, r)( status table, CAM(Content Addressable Memory), new CID table and partial packet memory. Also the designed receive unit supports the PCI interface with host processor. The receive unit is implemented in Xilinx FPGA and operates at 72MHz.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.41-44
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• 1987

Recently Hopfield proposed a model for content-addressable memory, which has been shown to be capable of storing information in a distributed fashion and determining the nearest-neighbor. Its application is, however, inherently limited to the case that the number of l's in each stored vector is nearly the same as the number of O's in that vector. If not the case, the model has high probability of failure in finding the nearest-neighbor. In this work, a modification of the Hopfield's model, which works well irrespective of the number of l's (or O's) in each stored vector, is suggested.