• Title/Summary/Keyword: Consumed-Power

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Development of 10-mN Class Hall Thruster and Its Performance Optimization through Numerical Analysis

  • Seon, Jong-Ho;Park, Jae-Heung;Lee, Jong-Sub;Lim, Yu-Bong;Seo, Mi-Hui;Choe, Won-Ho;Lee, Hae-June
    • Proceedings of the Korean Society of Propulsion Engineers Conference
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    • 2008.03a
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    • pp.550-552
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    • 2008
  • A small hall thruster with a thrust of about 10 mN and a specific impulse of about 1500 s is being developed with an intent to control or maintain the orbits of small satellites. The total mass, consumed electric power and efficiency of the thruster are approximately 10 kg, 300W and 30%, respectively. The thruster system consists of a hall thruster with a cylindrical cross section, a power processing unit and a Xenon(Xe) gas feed system. Laboratory examination of the thruster performance finds that the thruster meets the design specification.

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Energy-Efficient Ternary Modulator for Wireless Sensor Networks

  • Seunghan Baek;Seunghyun Son;Sunmean Kim
    • Journal of Sensor Science and Technology
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    • v.33 no.3
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    • pp.147-151
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    • 2024
  • The importance of Wireless Sensor Networks is becoming more evident owing to their practical applications in various areas. However, the energy problem remains a critical barrier to the progress of WSNs. By reducing the energy consumed by the sensor nodes that constitute WSNs, the performance and lifespan of WSNs will be enhanced. In this study, we introduce an energy-efficient ternary modulator that employs multi-threshold CMOS for logic conversion. We optimized the design with a low-power ternary gate structure based on a pass transistor using the MTCMOS process. Our design uses 71.69% fewer transistors compared to the previous design. To demonstrate the improvements in our design, we conducted the HSPICE simulation using a CMOS 180 nm process with a 1.8V supply voltage. The simulation results show that the proposed ternary modulator is more energy-efficient than the previous modulator. Power-delay product, a benchmark for energy efficiency, is reduced by 97.19%. Furthermore, corner simulations demonstrate that our modulator is stable against PVT variations.

A Constant Pitch Based Time Alignment for Power Analysis with Random Clock Power Trace (전력분석 공격에서 랜덤클럭 전력신호에 대한 일정피치 기반의 시간적 정렬 방법)

  • Park, Young-Goo;Lee, Hoon-Jae;Moon, Sang-Jae
    • The KIPS Transactions:PartC
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    • v.18C no.1
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    • pp.7-14
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    • 2011
  • Power analysis attack on low-power consumed security devices such as smart cards is very powerful, but it is required that the correlation between the measured power signal and the mid-term estimated signal should be consistent in a time instant while running encryption algorithm. The power signals measured from the security device applying the random clock do not match the timing point of analysis, therefore random clock is used as counter measures against power analysis attacks. This paper propose a new constant pitch based time alignment for power analysis with random clock power trace. The proposed method neutralize the effects of random clock used to counter measure by aligning the irregular power signals with the time location and size using the constant pitch. Finally, we apply the proposed one to AES algorithm within randomly clocked environments to evaluate our method.

Low Power Design of Filter Based Face Detection Hardware (필터방식 얼굴검출 하드웨어의 저전력 설계)

  • Kim, Yoon-Gu;Jeong, Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.89-95
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    • 2008
  • In this paper, we designed a low power face detection hardware and analysed its power consumption. The face detection hardware was fabricated using Samsung 0.18um CMOS technology and it can detect multiple face locations from a 2-D image. The hardware is composed of 6 functional modules and 11 internal memories. We introduced two operating modes(SLEEP and ACTIVE) to save power and a clock gating technique was used at two different levels: modules and registers. In additional, we divided an internal memory into several pieces to reduce the energy consumed when accessing memories, and fully utilized low power design option provided in Synopsis Design Compiler. As a result, we could obtain 68% power reduction in ACTIVE mode compared to the original design in which none of the above low power techniques were used.

Power Saving Mechanisms for LTE Base Stations Using Traffic Characteristic (Traffic 특성을 이용한 LTE 기지국의 Power Saving 메커니즘)

  • Lee, Seung-Hwan;Lee, Seung-Hyong
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.9 no.1
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    • pp.49-54
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    • 2010
  • 3GPP(Third Generation Partnership Project) LTE system that is the next step forward in cellular 3G services address the issues related to power saving at LTE base station. This is because that most of the energy in a typical telecommunication network is consumed by the wireless network's base station site. Power saving at LTE base station fall in with low-carbon green technology. This thesis proposes a power saving MAC protocol for LTE base station which utilizes different graded DRX/DTX(Discontinuous. Reception/Transmission). Considering traffic type in UE, proposed MAC protocol controls adaptive DRX/DTX cycle. The proposed method is more improve power saving performance than another method which is unchanged DRX/DTX by conditions. In this thesis, I propose an power saving MAC protocol in an environment where LTE base station are communicated with UE and prove improvement in performance through simulations.

Gated Clock-based Low-Power Technique based on RTL Synthesis (RTL 수준에서의 합성을 이용한 Gated Clock 기반의 Low-Power 기법)

  • Seo, Young-Ho;Park, Sung-Ho;Choi, Hyun-Joon;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.3
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    • pp.555-562
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    • 2008
  • In this paper we proposed a practical low-power design technique using clock-gating in RTL. An efficient low-power methodology is that a high-level designer analyzes a generic system and designs a controller for clock-gating. Also the desirable flow is to derive clock-gating in normal synthesis process by synthesis tool than to insert directly gate to clock line. If low-power is considered in coding process, clock is gated in coding process. If not considered, after analyzing entire operation. clock is Bated in periods of holding data. After analyzing operation for clock-gating, a controller was designed for it, and then a low-power circuit was generated by synthesis tool. From result, we identified that the consumed power of register decreased from 922mW to 543mW, that is the decrease rate is 42%. In case of synthesizing the test circuit using synthesizer of Power Theater, it decreased from 322mW to 208mW (36.5% decrease).

Design and Implementation of User Pattern based Standby Power Reduction System Applying Zigbee-MQTT in a Smart Building Environment (스마트빌딩 환경에서 Zigbee-MQTT를 이용한 사용자 패턴 기반 대기전력 저감 시스템 설계 및 구현)

  • Jang, Young-Hwan;Lee, Sang-Soon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.24 no.9
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    • pp.1158-1164
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    • 2020
  • In Korea, the dependence on imported energy is very high, and research to reduce standby power is being conducted based on Zigbee, a low-power technology, to reduce wasted power and improve power efficiency. However, because Zigbee is not an IoT standard protocol and is not network-based, it is necessary to build a network with a separate gateway, and research on standby power is insufficient because the standards for international power consumption of devices are ambiguous. Therefore, in this paper, we applied the IoT standard protocol MQTT to the existing Zigbee technology to build a network network without a separate gateway, and designed and implemented a standby power reduction system that collects standby power degradation and user patterns. As a result of evaluating with the existing system, it was confirmed that about 7.11% of standby power was consumed compared to the existing system.

A Study on the Cutting Optimal Power Requirements of Fast Growing Trees by Circular Saw (원형톱에 의한 속성수 절단 적정 소요동력 산정에 관한 연구)

  • Choi, Yun Sung;Kim, Dae Hyun;Oh, Jae Heun
    • Journal of Korean Society of Forest Science
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    • v.103 no.3
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    • pp.402-407
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    • 2014
  • In this study, Italy poplar(Populus euramericana) was selected for test specimen to measure cutting power when it harvested. The experiment has been controlled as three levels of feed rate (0.41, 1.25 and 2.5 m/s), sawing speed (800, 1,000 and 1,200 rpm), and the five levels of root collar diameter (50, 70, 90 and 110, 130 mm). The harvested volume after 3 years (root collar diameter 50 mm) was 10.5 tons, which falls short of the target amount of biomass is 20~30 ton/ha. In addition, the biomass amount of diameter 90 and 110 mm which reached the target amount were estimated to be 23.5 and 32.5 ton/ha respectively. As a result of experiment, it was found out that power of 128.2 and 175.8 W are consumed in case of cutting with the feed rate of 0.41m/s and minimum sawing speed (800 rpm) respectively. With the working area of 0.3 ha/h, it is considered to present working capacities of 16.5 and 22.8 ton/h respectively. The power consumed at the feed rate of 1.25 m/s is estimated to be 113.8 and 153.7W respectively and working capacity in a working area of 1 ha/h is estimated to be 23.5 and 32.5 ton/h. The power consumed at the feed rate of 2.5 m/s is estimated to be 119.8 and 166.9 W respectively and working capacity in a working area of 2 ha/h is estimated to be 47.0 and 65.5 ton/ha respectively. Therefore, the power source of harvest machine at the feed rate of 1.25, 2.50 m/s and sawing speed of 800 rpm shall be selected as it can process the target amount of estimated biomass.

An Analysis of Water Consumption Structures in Korean Industry Using the Input-Output Model (산업연관모형을 이용한 우리나라 산업의 직·간접 물소비 구조 분석)

  • Park, Chang-Gui;Lee, Ki-Hoon
    • Journal of Environmental Policy
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    • v.9 no.2
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    • pp.21-39
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    • 2010
  • In this paper, water consumption annually for industries in Korea was estimated for the first time and based on this, an input-output model was prepared for water consumption analysis. Also making use of this, the direct and indirect water consumption effect according to industrial activities was analyzed and the total effect based on volume was broken down into each factor. The amount of water consumed for industries in Korea (excluding agriculture, forestry and fishery) was estimated about 7 billion and 692 million ton in 2003(excluding sea water). Classifying by industry, the one for electric power & water service accounted for almost half, 49.5%, metalworking industry for 24.3% and chemical industry for 5.0%. As the result of estimation for the direct and indirect water consumption inducement coefficients, the amount of water consumed per the production of one million won ranked the highest for electric power & water service as 113.8 ton and the next highest ones ranked as 49.6 ton for the first metalworking, 16.8 ton for textile and leather goods, and 11.9 ton for general machinery respectively. In the meantime, as the result of breaking down into each factor of total amount of water consumed by industry, it appeared that the ripple effect having on other industries was more than the direct effect.

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A Study on Methodology to Improve the Power Factor of the High Power LED Module (고출력 LED 모듈 역률 개선 방법 연구)

  • Lho, Young Hwan
    • Journal of IKEEE
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    • v.18 no.3
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    • pp.335-340
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    • 2014
  • Recently, LED (Light Emitting Diode) becomes to be useful to apply for the lightening sources in electric systems and the lightening equipment since the power is less consumed with high efficiency, and the size and the weight of LED are small and light, respectively. The LED is controlled with constant current and SMPS (Switching Mode Power Supply). It is necessary for the LED manufacturer to secure the fundamental technology of designing LED chip, and to study the methodology to improve the power factor (PF) and to design the operational circuit for the development of LED to reduce the power loss in the application of LED lightening. The direct AC (Alternating Current) LED driving circuit, HV9910, is widely used in the industry field. In this paper, it is to evaluate the improved methodology for the power factor and efficiency through simulations when PFC (Power Factor Correction) and Noise Filter are added to HV9910.