• ETRI Journal
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• 제17권2호
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• pp.21-30
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• 1995

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

• 한국감성과학회:학술대회논문집
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• 한국감성과학회 2002년도 춘계학술대회 논문집
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• pp.221-228
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• 2002

The NAVER is based on a cluster of low-cost personal computers. The goal of NAVER is to provide flexible, extensible, scalable and re-configurable framework for the diverse virtual environments especially for Gamsung research experiments. Personal computers are divided into three servers are according to their specific functions: Render Server, Device Server and Control Server. While Device Server contains external modules requiring event-based communication for the integration, Control Server contains external modules requiring synchronous communication every frame. And, the Render Server consists of 5 managers: Scenario Manager, Event Manger, Command Manager, Interaction Manager and Sync Manager. In this paper, we discuss NAVER as effective distributed system and its application to Gamsung experiment.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제10권8호
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• pp.3701-3727
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• 2016

Recently Service Function Chaining (SFC) is promising to innovate the network service mode in modern networks. However, a feasible implementation of SFC is still difficult due to the need to achieve functional equivalence with traditional modes without sacrificing performance or increasing network complexity. In this paper, we present a configurable network service chaining (CNSC) mechanism to provide services for network traffics in a flexible and optimal way. Firstly, we formulate the problem of network service chaining and design an effective service chain construction framework based on integrating software-defined networking (SDN) with network functions virtualization (NFV). Then, we model the service path computation problem as an integer liner optimization problem and propose an algorithm named SPCM to cooperatively combine service function instances with a network utility maximum policy. In the procedure of SPCM, we achieve the service node mapping by defining a service capacity matrix for substrate nodes, and work out the optimal link mapping policies with segment routing. Finally, the simulation results indicate that the average request acceptance ratio and resources utilization ratio can reach above 85% and 75% by our SPCM algorithm, respectively. Upon the prototype system, it is demonstrated that CNSC outperforms other approaches and can provide flexible and scalable network services.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권3호
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• pp.207-220
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• 2011

Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제15권5호
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• pp.1829-1846
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• 2021

Transient faults occur in computation units of a processor, which can cause control flow errors (CFEs) and compromise system reliability. The software-based methods perform illegal control flow detection by inserting redundant instructions and monitoring signature. However, the existing methods not only have drawbacks in terms of performance overhead, but also lack of configurability. We propose a configurable approach CCFCA for detecting CFEs. The configurability of CCFCA is implemented by analyzing the criticality of each region and tuning the detecting granularity. For critical regions, program blocks are divided according to space-time overhead and reliability constraints, so that protection intensity can be configured flexibly. For other regions, signature detection algorithms are only used in the first basic block and last basic block. This helps to improve the fault-tolerant efficiency of the CCFCA. At the same time, CCFCA also has the function of solving confusion and instruction self-detection. Our experimental results show that CCFCA incurs only 10.61% performance overhead on average for several C benchmark program and the average undetected error rate is only 9.29%. CCFCA has high error coverage and low overhead compared with similar algorithms. This helps to meet different cost requirements and reliability requirements.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2009년도 추계학술대회 논문집
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• pp.723-724
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• 2009

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권2호
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• pp.786-799
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• 2018

Recently, NFV has attracted attention as a next-generation network virtualization technology for hardware -independent and efficient utilization of resources. NFV is a technology that not only virtualize computing, server, storage, network resources based on cloud computing but also connect Multi-Tenant of VNFs, a software network function. Therefore, it is possible to reduce the cost for constructing a physical network and to construct a logical network quickly by using NFV. However, in NFV, when a new VNF is added to a running Tenant, authentication between VNFs is not performed. Because of this problem, it is impossible to identify the presence of Fake-VNF in the tenant. Such a problem can cause an access from malicious attacker to one of VNFs in tenant as well as other VNFs in the tenant, disabling the NFV environment. In this paper, we propose Auto-configurable Security Mechanism in NFV including authentication between tenant-internal VNFs, and enforcement mechanism of security policy for traffic control between VNFs. This proposal not only authenticate identification of VNF when the VNF is registered, but also apply the security policy automatically to prevent malicious behavior in the tenant. Therefore, we can establish an independent communication channel for VNFs and guarantee a secure NFV environment.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제16권12호
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• pp.1259-1263
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• 2010

SaaS는 소프트웨어 개발 및 배포에 있어 전체적인 비용을 크게 줄일 수 있는 새로운 패러다임으로 분산 컴퓨팅, 그린 컴퓨팅, 클라우드 컴퓨팅 동의 최신 컴퓨팅 플랫폼에 있어 중요한 기반기술로 여겨지고 있다. 이러한 SaaS는 기존의 소프트웨어와 달리 높은 수준의 설정 가능성(Configurability)을 요구받고 있으며, 이에 따라 설정 요구사항(Configuration Requirements)의 추출에 있어 모든 설정 가능성을 빠짐 없이 고려하는 것이 매우 중요하다. 본 연구에서는 SaaS의 특성에 따라 각 요구사항에 대한 설정 가능성이 누락되지 않도록 결정할 수 있는 분류 기법을 제안한다.

• 한국통신학회논문지
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• 제28권11A호
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• pp.936-944
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• 2003

본 논문에서는 FPGA (Field Programmable Gate Array)에 사용될 수 있는 AND/XOR기반의 기술적인 매핑 기법이 제안되었다. FPGA에서는 프로그램 블록들의 숫자가 정해져 있기 때문에 적절한 수의 입력을 가진 블록으로 회로를 나눌 수 있으면 효과적인 구현이 가능하다. Davio Expansion에 기반한 제안된 기법은 Davio Expansion 자체가 AND/XOR의 성질을 가지고 있기 때문에 XOR를 많이 포함하고 있는 에러 검출/수정, 데이터 암호/해독, 산술 회로 등을 구현하기 매우 용이하다. 본 논문에서는 제안된 기법을 이용할 때 구현되는 면적뿐만 아니라 속도도 현저히 저하될 수 있음을 MCNC 벤치마크를 이용하여 증명하였다. 면적이 줄어듦을 보이기 위하여 CLB (Configurable Logic Block) 숫자와 총 게이트 숫자가 이용되었다. CLB 숫자는 67.6 % (속도로 최적화 된 결과)와 57.7 % (면적으로 최적화 된 결과) 만큼 감소되었고 총 게이트 숫자는 65.5 %만금 감소되었다. 속도관련 결과를 확인하기 위해 사용된 최대 Path Delay는 현재 사용되고 있는 방법들에 비해 56.7 %만큼 감소되었고 최대 Net Delay는 80.5% 만큼 감소되었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.381-384
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• 2001

This paper describes the features and development of a RAM compiler that can generate low power, high speed, synchronous CMOS SRAM. The compiled SRAM can be configurable from 64bytes to 16Kbytes in one bank and has 2ns access time typically. Basic cells are developed using 2-poly, 4-metal 0.35um CMOS technology. This SRAM compiler is developed using SKIL $L^{TM}$ language and generates layout and schematic in Cadence environment.