• Communications of the Korean Institute of Information Scientists and Engineers
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• v.1 no.1
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• pp.75-79
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• 1983

現代 컴퓨터의 연산장치(Arithmetic unit)의 design을 하는데 있어서 가장 중요하게 요구점점되는 點은 계산의 속도(Computational speed)와 計算의 정확성 (Computational accuracy)이라고 보겠다. 여기서는 정보처리기(Information processor)로서 또는 非數理的인 연산(Non-numeric operation)을 위한 도구로서 보다는 數理的 연산(Arithmetic)을 수행하는 도구로서의 컴퓨터 연산에 限해서만 論하고자 한다. 대개의 경우 기계를 고안하는 사람들은 계사의 속도에 對해서는 특별한 관심을 갖고 그러한 목적에 맞는 기계를 만들어 낼려고 하지만 數値의 정 확성(Numerical accuracy)에 對해서ㅡ 등한시했던 경우가 많았다고 보겠다. 그러 나 이 두 條件 즉 빠른 속도 틀림없는 정확성을 同時에 충족 시키고자 하는 것이 기계 고안자들의 理想 목포가 되는 것은 사시링다. 여기에 수반도는 문제는 제작 비를 고려하지 않을 수 없다는 것이다. 정화하고 빠른 operation을 할 수 있는 기 계는 너무 비싼 제작비가 들기 때문에 사용목적에 적절하게 두 문제를 절충하여 고려하는 것이 일반적이라 하겠다. 初期의 컴퓨터는 한 Word(Computer Word)로 서 36개의 bit를 사용한 것이 많았다고 본다. 그러나 1961년 4月 Tennessee에서 Oak Riage National Laboratory와 The Society for Industril and Applied Mathematics 후원하에 일주일에 걸친 국제회의가 열렸었는데 거기 모인 거의 모 든 學者들이 앞으로의 과학 연구용 컴퓨터(Scientific Computer)의 한 Word의 길 이는 적어도 48bit 이상으로 증가시켜야 된다는데 의견을 모았었다고 한다. 이제 rounding error의 성향(begavior)을 알아보기 위한 간단한 例를 들어 봄으로써 이 글을 쓰는 동기으 일면을 대신하고자 한다.

• Journal of the Korean Mathematical Society
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• v.51 no.2
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• pp.383-402
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• 2014

We expose a pattern for establishing Friedman-Weiermann style independence results according to which there are thresholds of provability of some parameterized variants of well-partial-ordering. For this purpose, we investigate an ordinal notation system for ${\vartheta}{\Omega}^{\omega}$, the small Veblen ordinal, which is the proof-theoretic ordinal of the theory $({\prod}{\frac{1}{2}}-BI)_0$. We also show that it sometimes suffices to prove the independence w.r.t. PA in order to obtain the same kind of independence results w.r.t. a stronger theory such as $({\prod}{\frac{1}{2}}-BI)_0$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.42-46
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• 2010

Encapsulation for information security is often carried out in Galois field in the form of arithmetic operations. This paper proposes how to efficiently perform exponentiation of arithmetic information on Galois field. Especially, by improving an existing bit-parallel exponentiator to exclude elements with heavy gate counts and to take advantage of system constants, this paper proposes how to implement a VLSI architecture with high performance even for large m.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.675-686
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• 2005

This paper proposes a new method of mathematically modeling and computer simulating television ghosts wherein television signals that have undergone multipath fading are generated without using approximations by considering the attenuation, time delay, phase, and timing jitter between consecutive frames. Conventional methods used polynomial interpolation or complex arithmetic to take into account the ghost phase, but our method uses only real arithmetic by employing the Hilbert transform and also reduces the computation time using the FFT (fast Fourier transform) algorithm. Furthermore, it is also possible to observe the transmit waveforms in both RF and IF ranges. Various ghost patterns generated in software provide for essential data required for the development of ghost canceling algorithms, and are deemed to be very useful in analyzing the constituent blocks of the transmitter and receiver chain in television broadcasting. The development of ghost cancelers needs to be preceded by the task of mathematically modeling ghosts and their extensive computer simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.57-67
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• 2005

Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.

• International journal of advanced smart convergence
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• v.6 no.2
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• pp.24-33
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• 2017

Since 'teaching coding' or 'programming' classes for computational thinking (CT) education in K-12 are renowned around the world, a pre-service teachers' readiness for integrating CT into their teaching subjects is important due to the fact that CT is considered to be another 'R' from algoRitm for 21st century literacy, in addition to the traditional 3R (Reading, Writhing, and Arithmetic) [2] and CT roles to other disciplines. With this rationale, we designed a guided instruction based CT course for pre-service teachers. We show the effectiveness of the program with respect to the teachers' attitude toward combining CT into their teaching subjects, and mindset changes of learning computing connected with the career development of the teacher themselves. The research focused on the instructional methodology of teaching programing for non-Computer Science Education (CSE) majors who are not familiar with computer science for alleviating the cognitive load of first exposure to programming course under the CT concepts.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.333-336
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• 2000

We discuss the direct methods (Gauss-Jordan and Gaussian eliminations) to solve linear systems on distributed memory parallel computers. It will be shown that the so-called row-cyclic storage gives rise to the best performance among the standard three (row-cyclic, column-cyclic and cyclic-cyclic) data storages. We also show that Gauss-Jordan elimination, rather than Gaussian elimination, is highly efficient for the direct solution of linear systems in parallel processing, though Gauss-Jordan elimination requires a larger number of arithmetic operations than Gaussian elimination. Numerical experiment is performed on HITACHI SR12201 with the standard libraries MPI and BLAS.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.263-264
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of 0.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation or in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA implementation results for the proposed structure show 39% and 32% gate count reduction comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.437-440
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• 2009

We propose a fast stream cipher ASC16 for software implementation. ASC16 has a very simple structure with ASR(Arithmetic Shift Register), NLF(Non-Linear Filter), and NLB(Non-Linear Block), and is executed by a word. It is a stream cipher for wireless communication, which makes 32bit key streams using s-box with non-linear transformation. The processed result is almost same as SSC2, 32bit output stream cipher, developed by Zhang, Carroll, and Chan. The period is longer than SSC2, and it causes the difficulty of Correlation attack and raises security very much. The proposed ASC16 is efficiently used in the process of a fast cipher in the limited environment such as wireless communication.

• Journal of The Korean Association of Information Education
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• v.15 no.4
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• pp.635-644
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• 2011

This research analyzed the brainwave activities and brain hemispherity to find out any implications to design the connections between the activities of the brain function and the computerized arithmetic addition in two difficulty levels: easy: 1-5 vs. hard: 6-9. Thus, in developing the brain based math learning for the computer education by implicit association test(IAT) indicated the significant results for the exclusive brain location and the brain hemispherity on the theta, alpha, low alpha, beta brainwaves by QEEG analysis. The results of this study physiologically supported the theoretical background for the computerized math learning skills as well as the math learning material development. It shows the difficulty levels of math information education and the brain activities on cognitive process of the learner continued on the possible investigation of the brain science.