• Proceedings of the Korean Society of Precision Engineering Conference
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• 1992.04a
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• pp.127-132
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• 1992

To relize the future intelligent robot the development of a special-purpose processor for a coordinate transformation is evidently challenging task. In this case the complexity of a hardware architecture strongly depends on the adopted algorithm. In this paper we have used an inverse kinemetics algorithm based on incremental unit computation method. This method considers the 3-axis articulated robot as the combination of two types of a 2-axis robot: polar robot and 2-axis planar articulated one. For each robot incremental units in the joint and Cartesian spaces are defined. With this approach the calculation of the inverse Jacobian matrix can be realized through a simple combinational logic gate. Futhermore, the incremental computation of the DDA integrator can be used to solve the direct kinematics. We have also designed a hardware architecture to implement the proposed algorithm. The architecture consists of serveral simple unitsl. The operative unit comprises several basic operators and simple data path with a small bit-length. The hardware architecture is realized byusing the EPLD. For the straight-line motion of the KAIST arm we have obtained maximum end effector's speed of 12.6 m/sec by adopting system clock of 8 MHz.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• Journal of Internet Computing and Services
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• v.7 no.1
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• pp.49-57
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 12B-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array, This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.291-297
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.409-412
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• 2003

In this paper, the encoder architecture of 3-D wavelet transform based on lifting scheme is designed. Architecture, here, 3 level wavelet transform for spatial decomposition and 2 level wavelet transform for temporal decomposition is adopted with efficient computation.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.57-60
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• 2000

This paper presents a new adaptive fast motion estimation algorithm along with its architecture. The conventional algorithm such as full - search algorithm, three step algorithm have some disadvantages which are related to the amount of computation, the quality of image and the implementation of hardware, the proposed algorithm uses spatial correlation and a slope of motion vector in order to reduce the amount of computation and preserve good image quality, The proposed algorithm is better than the conventional Block Matching Algorithm(BMA) with regard to the amount of computation and image quality. Also, we propose an efficient at chitecture to implement the proposed algorithm. It is suitable for real time processing application.

• Journal of the Korean Professional Engineers Association
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• v.42 no.6
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• pp.28-30
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• 2009

There is a proverb in Korea "Don't chase after another." It can be a right proverb in sometimes. However, usually it doesn't fit in these various society, information knowledge society. Modern society requires convergence technology. IBS (Intelligent Building System) requires knowledge of architecture field, electric field, communication field, and computation field. ITS (Intelligent Transport Systems) which is constructing in many cities requires various knowledge as engineering works, electricity, computation, communication and transportation. In the case of u-City, it requires technology of many fields as architecture, electricity, communication, engineering works, transportation, and computation. Anyone who wants to participate in u-City should study and acquire knowledge in various field. Otherwise, it must be failed because of lack of communication like as the Tower of Babel. U-City is not a portion of one field. Therefore, engineers in many fields should cooperate with each other to make u-city as the best product in the world.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.2
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• pp.106-112
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• 2007

This paper proposes a hybrid architecture algorithm for fast computation of DCT and DFT via recursive factorization. Recursive factorization of DCT-II and DFT transform matrix leads to a similar architectural structure so that common architectural base may be used by simply adding a switching device. Linking between two transforms was derived based on matrix recursion formula. Hybrid acrchitectural design for DCT and DFT matrix decomposition were derived using the generation matrix and the trigonometric identities and relations. Data flow diagram for high-speed architecture of Cooley-Tukey type was drawn to accommodate DCT/DFT hybrid architecture. From this data flow diagram computational complexity is comparable to that of the fast DCT algorithms for moderate size of N. Further investigation is needed for multi-mode operation use of FFT architecture in other orthogonal transform computation.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.8 no.2
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• pp.678-690
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• 2014

The current networks do not disclose information about a management domain due to scalability, manageability and commercial reasons. Therefore, it is very hard to calculate an optimal path to the destination. Also, due to poor information sharing, if an error occurs in the intermediate path, it is very difficult to re-search the path and find the best path. Hence, to manage each domain more efficiently, an architecture with top-level path computation node which can obtain information of separate nodes are highly needed This study aims to investigate a federation of a united network around NRN(National Research Network) that could allow resource sharing between countries and also independent resource management for each country. Considering first the aspects that can be accessed from the perspective of a national research network, ICE(Information Control Element) and GFO(Global Federation Organizer)-based architecture is designed as a top-level path computation element to support traffic engineering and applied to the multi-domain network. Then, the federation for the independent management of resources and resource information sharing among national research networks have been examined.