• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 1992년도 춘계학술대회 논문집
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• pp.127-132
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• 1992

To relize the future intelligent robot the development of a special-purpose processor for a coordinate transformation is evidently challenging task. In this case the complexity of a hardware architecture strongly depends on the adopted algorithm. In this paper we have used an inverse kinemetics algorithm based on incremental unit computation method. This method considers the 3-axis articulated robot as the combination of two types of a 2-axis robot: polar robot and 2-axis planar articulated one. For each robot incremental units in the joint and Cartesian spaces are defined. With this approach the calculation of the inverse Jacobian matrix can be realized through a simple combinational logic gate. Futhermore, the incremental computation of the DDA integrator can be used to solve the direct kinematics. We have also designed a hardware architecture to implement the proposed algorithm. The architecture consists of serveral simple unitsl. The operative unit comprises several basic operators and simple data path with a small bit-length. The hardware architecture is realized byusing the EPLD. For the straight-line motion of the KAIST arm we have obtained maximum end effector's speed of 12.6 m/sec by adopting system clock of 8 MHz.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2005년도 춘계학술발표대회
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• 인터넷정보학회논문지
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• 제7권1호
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• pp.49-57
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• 2006

본 논문에서는 128-bit 블록암호인 SEED 알고리즘을 하드웨어로 구현하는데 있어서 면적을 줄이고 연산속도를 증가시키는 회로구조에 대하여 논하였고 설계결과를 기술하였다. 연산속도를 증가시키기 위해 pipelined systolic array 구조를 사용하였으며, 입출력회로에 어떤 버퍼도 사용하지 않는 간단한 구조이다. 이 회로는 10 MHz 클럭을 사용하여 최대 320 Mbps의 암호화속도를 달성할 수 있다. 회로설계는 VHDL 코딩방식으로 수행하였으며, 50,000 gates 급의 FPGA에 구현하였다.

• 한국정보통신학회논문지
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• 제10권2호
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• pp.291-297
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• 2006

본 논문에서는 128-bit 블록암호인 SEED 알고리즘을 하드웨어로 구현하는데 있어서 면적을 줄이고 연산속도를 증가시키는 회로구조에 대하여 논하였고 설계결과를 기술하였다. 연산속도를 증가시키기 위해 Pipelined systolic array 구조를 사용하였으며, 입출력 회로에 어떤 버퍼도 사용하지 않는 간단한 구조이다. 이 회로는 10 MHz 클럭을 사용하여 최대 320 Mbps의 암호화 속도를 달성할 수 있다. 회로설계의 목표를 고속 암호화와 회로구조의 단순화에 두었다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(4)
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• pp.57-60
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• 2000

This paper presents a new adaptive fast motion estimation algorithm along with its architecture. The conventional algorithm such as full - search algorithm, three step algorithm have some disadvantages which are related to the amount of computation, the quality of image and the implementation of hardware, the proposed algorithm uses spatial correlation and a slope of motion vector in order to reduce the amount of computation and preserve good image quality, The proposed algorithm is better than the conventional Block Matching Algorithm(BMA) with regard to the amount of computation and image quality. Also, we propose an efficient at chitecture to implement the proposed algorithm. It is suitable for real time processing application.

• 기술사
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• 제42권6호
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• pp.28-30
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• 2009

There is a proverb in Korea "Don't chase after another." It can be a right proverb in sometimes. However, usually it doesn't fit in these various society, information knowledge society. Modern society requires convergence technology. IBS (Intelligent Building System) requires knowledge of architecture field, electric field, communication field, and computation field. ITS (Intelligent Transport Systems) which is constructing in many cities requires various knowledge as engineering works, electricity, computation, communication and transportation. In the case of u-City, it requires technology of many fields as architecture, electricity, communication, engineering works, transportation, and computation. Anyone who wants to participate in u-City should study and acquire knowledge in various field. Otherwise, it must be failed because of lack of communication like as the Tower of Babel. U-City is not a portion of one field. Therefore, engineers in many fields should cooperate with each other to make u-city as the best product in the world.

• 전자공학회논문지A
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• 제30A권3호
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 신호처리소사이어티 추계학술대회 논문집
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• pp.409-412
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• 2003

In this paper, the encoder architecture of 3-D wavelet transform based on lifting scheme is designed. Architecture, here, 3 level wavelet transform for spatial decomposition and 2 level wavelet transform for temporal decomposition is adopted with efficient computation.

• 융합신호처리학회논문지
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• 제8권2호
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• pp.106-112
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• 2007

본 논문은 순환 행렬 분해에 의한 DCT와 DFT의 고속 계산을 위한 하이브리드 아키텍쳐 알고리듬을 제안한다. DCT-II와 DFT 변환 행렬의 순환 분해는 알고리듬적으로 구현하기가 유사한 구조를 제공하며 이것은 단순히 스위칭 모드의 제어에 의해 공통 아키텍쳐를 사용할 수 있게 한다. 두 변환간의 연계는 행렬 순환 공식에 기초하여 유도되었다. DCT/DFT 행렬 분해를 위한 하이브리드 구조 설계를 가능하도록 생성 행렬, 삼각함수 항등식 과 관계식을 사용하여 유도되었다. DCT/DFT 하이브리드 아키텍쳐를 수용하는 쿨리-투키 유형의 고속처리 아키텍쳐에 대한 데이터 흐름도를 작성하였다. 이 데이터 흐름도로부터 적절한 크기의 N에 대해 제안한 알고리듬의 계산 복잡도는 기존의 고속 DCT 알고리듬과 비교할만하다. 다른 직교변환 계산에 FFT 구조의 다중 모드 사용 확장을 위해 좀더 확장된 연구가 필요하다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제8권2호
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• pp.678-690
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• 2014

The current networks do not disclose information about a management domain due to scalability, manageability and commercial reasons. Therefore, it is very hard to calculate an optimal path to the destination. Also, due to poor information sharing, if an error occurs in the intermediate path, it is very difficult to re-search the path and find the best path. Hence, to manage each domain more efficiently, an architecture with top-level path computation node which can obtain information of separate nodes are highly needed This study aims to investigate a federation of a united network around NRN(National Research Network) that could allow resource sharing between countries and also independent resource management for each country. Considering first the aspects that can be accessed from the perspective of a national research network, ICE(Information Control Element) and GFO(Global Federation Organizer)-based architecture is designed as a top-level path computation element to support traffic engineering and applied to the multi-domain network. Then, the federation for the independent management of resources and resource information sharing among national research networks have been examined.