• 전력전자학회논문지
• /
• 제20권4호
• /
• pp.313-320
• /
• 2015

This study deals with a bidirectional interleaved soft switching DC-DC converter for a wide range of input voltages. The proposed converter operates in complementary switching with the purpose of inductor size reduction and zero-voltage switching (ZVS) operation. The current ripple related to complementary switching is minimized by three-phase interleaved operation. The main characteristics of the proposed topology are its soft-switching method of operation and its simple structure. The soft-switching operation and the system efficiency of the proposed converter are verified by experimental results.

• 한국조명전기설비학회지:조명전기설비
• /
• 제9권5호
• /
• pp.51-56
• /
• 1995

The transistors of single phase 3 level PWM Inverter compose output power transistors and neutral point clamping transistors, which are NPN transistors. Waveforms of driving signals for this are PWM waves for power transistors and period operating waves for neutral point clamping transistors, which signals made W-type modulation from rectangular and sine wave. The output power transistors operate at ON-time complementary and neutral point clamping transistors operate at OFF-time complementary respectively. Therefore, each transistors operate in half period at parallel. Characteristics of this inverter circuit is parallel switching method about series switching method of general inverter. As modulation of 3 level drive signals made from full-wave rectifier of sine wave and rectangular wave, which are level wave about 3 level of complementary transistor inverter. So, this circuit composed complementary operation inverter of NPN transistors only compare with PNP-NPN complementary inverter, which have high power 3 level inverter of complementary operation.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권2호
• /
• pp.227-234
• /
• 2014

A transceiver for a high-speed inductive-coupling link is proposed. The bi-phase modulation (BPM) signaling scheme is used due to its good noise immunity. The transmitter utilizes a complementary switching method to remove glitches in transmitted data. To increase the timing margin on the receiver side, an integrating receiver with a pre-charging equalizer is employed. The proposed transceiver was implemented via a 130-nm CMOS process. The measured timing window for a $10^{-12}$ bit error rate (BER) at 1.8 Gb/s was 0.33 UI.

• International Journal of Naval Architecture and Ocean Engineering
• /
• 제11권1호
• /
• pp.584-596
• /
• 2019

This paper presents a Modified Adaptive Complementary Sliding Mode Control (MACSMC) system for the longitudinal motion control of the Fully-Submerged Hydrofoil Craft (FSHC) in the presence of time varying disturbance and uncertain perturbations. The nonlinear disturbance observer is designed with less conservatism that only boundedness of the derivative of the disturbance is required. Then, a complementary sliding mode control system combined with adaptive law is designed to reduce the bound of stabilization error with fast convergence. In particularly, the modified complementary sliding mode surface which contains the estimation of the disturbance can reduce the switching gain and retain the normal performance of the system. Moreover, a hyperbolic tangent function contained in the control law is utilized to attenuate the chattering of the actuator. The global asymptotic stability of the closed-loop system is demonstrated utilizing the Lyapunov stability theory. Ultimately, the simulation results show the effectiveness of the proposed approach.

• 센서학회지
• /
• 제28권2호
• /
• pp.71-75
• /
• 2019

This paper proposes the extension of the dynamic range in complementary metal oxide semiconductor (CMOS) image sensors (CIS) using switching operation of in-pixel inverter. A CMOS inverter is integrated in each unit pixel of the proposed CIS for switching operations. The n+/p-substrate photodiode junction capacitances are added to each unit pixel. When the output voltage of the photodiode is less than half of the power supply voltage of the CMOS inverter, the output voltage of the CMOS inverter changes from 0 V to the power supply voltage. Hence, the output voltage of the CMOS inverter is adjusted by changing the supply voltage of the CMOS inverter. Thus, the switching point is adjusted according to light intensity when the supply voltage of the CMOS inverter changes. Switching operations are then performed because the CMOS inverter is integrated with in each unit pixel. The proposed CIS is composed of a pixel array, multiplexers, shift registers, and biasing circuits. The size of the proposed pixel is $10{\mu}m{\times}10{\mu}m$. The number of pixels is $150(H){\times}220(V)$. The proposed CIS was fabricated using a $0.18{\mu}m$ 1-poly 6-metal CMOS standard process and its characteristics were experimentally analyzed.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1989년도 하계종합학술대회 논문집
• /
• pp.515-517
• /
• 1989

This PWM inverter are used bridge circuit of two pair complementary transistor at each phase. The operation signals are 3 level PWM wave of W type and M type modulation, Which were obtained from switching time data by switching position calculation of triangular and sine wave. The output voltage waveforms of this inverter have the 5 level phase voltage and the 9 level line voltage of PWM.

• 대한전기학회논문지
• /
• 제39권2호
• /
• pp.157-163
• /
• 1990

The PWM inverter investigated in this paper utilizes a bridge type current sharing reactor circuit with tow pairs of complementary transistor at each phase. The driving signals for this inverter are 3 level PWM waves of W type an M type modulation, which are obtained from a microprocessor based on the switching time data obtained by switching position calculation of triangular and sine modulation wave. The output voltage waveforms of this inverter have 5 level phase voltage and 9 level line voltage of PWM. The harmonics of the output voltage are reduced to half when it is compared with single CTI, and the occurrence of harmonics is also reduced.

• 대한전자공학회논문지SD
• /
• 제48권12호
• /
• pp.37-44
• /
• 2011

본 논문은 BPM 방식의 신호전송을 하는 인덕티브 커플링 링크에서 전송속도를 증가시키고 BER를 개선하는 방법에 대하여 기술하였다. 데이터가 전송될 때 발생하는 불필요한 glitch를 제거하기 위해 상보적으로 스위칭하는 송신기를 사용하였고, 수신된 데이터의 최적화를 위해 pre-distortion 개념을 도입하였다. 또한 고속 동작에서 샘플링 가능구간을 확보하기 위해 적분형 수신기를 사용하였고, 빠른 pre-charge를 위해 수신기 내부의 적분기와 비교기의 pre-charge 경로에 이퀄라이징 트랜지스터를 추가하였다. 0.13 um CMOS 공정을 사용하여 설계한 송수신회로는 1.2 V 인가전압에서 2.4 Gb/s의 전송속도를 가질 때 약 5.99 mW의 전력소모를 가진다.

• E2M - 전기 전자와 첨단 소재
• /
• 제9권7호
• /
• pp.690-695
• /
• 1996

We have systematically investigated the characterization of V$_{2}$O$_{5}$ thin films as a counter electrode for lithium based complementary electrochromic devices. The V$_{2}$O$_{5}$ thin films were prepared by thermal vacuum evaporation with varing the substrate temperature and film thickness. In electrochromic devices for smart windows, the WO$_{3}$ thin films with 400-800 nm thickness require to be capable of reversibly injection 10-15 mC/cm$^{2}$ of lithium, which is readily accomplished charge-balanced switching in a V$_{2}$O$_{5}$ thin films with 100-150nm thick. The V$_{2}$O$_{5}$ thin films produces considerably small changes in optical modulation properties in the visible and near infrared region(500-1100 nm) compared to the amorphous WO$_{3}$ thin films on 10-15 mC/cm$^{2}$ of lithium injection and the V$_{2}$O$_{5}$ thin films can therefore act as a counter electrode to WO$_{3}$ in a lithium based complementary clectrochromic devices. After 10$^{5}$ coloration/bleaching switching time, the degradation does not occurs and the devices exhibit a stable optical modulation in V$_{2}$O$_{5}$ thin films. It has shown that the injected lithium ion amounts in crystalline V$_{2}$O$_{5}$ thin films with the same thickness is large by 3-5 mC/cm$^{2}$ of lithium compared to the amorphous thin films in the same driving conditions. Therefore, to optimize the device performance, it is necessary to choose an appropriate film thickness and crystallinity of V$_{2}$O$_{5}$ for amorphous WO$_{3}$ film thickness as a working electrode.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 1997년도 전력전자학술대회 논문집
• /
• pp.101-110
• /
• 1997

The circuit effects due to the transformer primary side series equivalent inductance in the Zero Voltage Switching Pulse Width Modulated Half Bridge DC/DC Converter and its impact on the effective duty are analyzed. The steady state equations and the small signal model of the converter are derived incorporating the effects of the complementary control and the utilization of transformer primary side series equivalent inductance. The open plant dynamics are analyzed on the basis of the model derived. The model predictions are confirmed by experimental measurements.