• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.1-7
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• 2006

An on chip voltage down converter (VDC) using the self temperature-compensation techniques is proposed. At a different gate bias voltage, PMOSFET shows different source to drain current characteristic according to the temperature variation. The proposed VDC can reduce its temperature dependency by the source to drain current ratio of two PMOSFET with different gate bias respectively. Proposed circuit is fabricated in Dongbu-anam $0.18{\mu}m$ CMOS process and experimental results show its temperature dependency of $-0.49mV/^{\circ}C$ and external supply dependency of 6mV/V. Total current consumption is only $1.1{\mu}A@2.5V$.

• Journal of the Korea Convergence Society
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• v.7 no.3
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• pp.77-85
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• 2016

We propose a digital signal processing technic that can compensate the non-linearity inherent in audio amplifiers, and present the result of the simulation. The inherent non-linearity of the audio power amplifier arising from analog devices is compensated via a digital signal processing technic consisting of indirect learning architecture and an adaptive filter. The simulation results show that the compensator can be realized using a third-order polynomial and compensates odd-order non-linearity efficiently. The even-oder non-linearity is mainly due to the dc offset at the output, which is difficult to eliminate with the proposed method. Care must be taken in designing the bias circuit to avoid the DC offset at the output. The proposed technic has significance in that digital signal processing technic can compensate for the impairment that is an inherent characteristic of an analog system.

• International Journal of Precision Engineering and Manufacturing
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• v.9 no.3
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• pp.27-32
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• 2008

This paper describes a contact atomic force microscope (AFM) that can be used for high-speed precision measurements of microstructured surfaces. The AFM is composed of an air-bearing X stage, an air-bearing spindle with the axis of rotation in the Z direction, and an AFM probe unit. The traversing distance and maximum speed of the X stage are 300 mm and 400 mm/s, respectively. The spindle has the ability to hold a sample in a vacuum chuck with a maximum diameter of 130 mm and has a maximum rotation speed of 300 rpm. The bandwidth of the AFM probe unit in an open loop control circuit is more than 40 kHz. To achieve precision measurements of microstructured surfaces with slopes, a scanning strategy combining constant height measurements with a slope compensation technique is proposed. In this scanning strategy, the Z direction PZT actuator of the AFM probe unit is employed to compensate for the slope of the sample surface while the microstructures are scanned by the AFM probe at a constant height. The precision of such a scanning strategy is demonstrated by obtaining profile measurements of a microstructure surface at a series of scanning speeds ranging from 0.1 to 20.0 mm/s.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.261-265
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• 2005

This paper describes the DC-DC Converter for Ancillary Power Supply in Hybrid Electric Vehicle. DC-DC Converter is used for charging 12V auxiliary battery supplying electric power to head ramp, audio, ECU etc in automobiles. used DC-DC Converter Topology is PS-ZVS FB(Phase Shifted Zero Voltage Switching Full-Bridge) to reduce switching loss and EMI noise induced by high frequency operating condition. And For easy compensation and stable system response characteristic, current mode control method including slope compensation is employed. Constant current / constant voltage charging control method guarantee stable electric charging of auxiliary battery. Simulation toll PSIM6.0 is used for initial circuit parameter settings and H/W debuging. Thermal problems of Switching components in DC-DC Converter is improved by using Thermo Tracer.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.10
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• pp.2066-2070
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• 2009

A voltage controlled attenuator using a PIN diode and two resistors of the $\pi$-type fixed attenuator is described in this paper. The proposed variable attenuator operating for a fixed attenuation range has a good input VSWR and a low intermodulation signal. For the low phase shift, a PIN diode is connected with open stub for the purpose of phase compensation. The stub for phase compensation is calculated by the Deloach method and the related circuit theory. This attenuator is easily fabricated on the microstrip and can be normally used in fine control circuits within small attenuation range. The fabricated attenuator for 2110~2170 MHz frequency band has about 4 dB of an attenuation range, $2^{\circ}$ of phase variance, and -20 dB of S11 according to the input voltage from 0 to 2.7 V.

• KSCE Journal of Civil and Environmental Engineering Research
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• v.31 no.1C
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• pp.29-38
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• 2011

The smaller diameter cone penetrometer has been widely used to estimate the characteristics of local area due to high vertical resolution. The half-bridge cirucits have been adopted to measure the mechnical strength of soil through the smaller diameter cone penetrometer due to the limitation of the areas for configuring the full-bridge circuit. The half-bridge circuit, however, is known as being easily affected to the temperature variation. The objective of this study suggests the temperature-compensated method in mini-cones. The diameter and length of the mini-cone is designed to 15mm and 56mm. The load cell of the mini-cone is extended about 54mm on the behind of the mini-cone to reflect the only temperature variation. The full-bridge circuit is installed to measure the temperature-compensated values in the mini-cone and the half-bridge circuit is also organized to compare the temperature compensated values with uncompensated values. The seasonal variation tests are performed to define the effect of temperature variation under summer and winter temperature condition. The densification tests are also carried out to investigate temperature effects during penetration. The measured mechanical resistances with temperature-compensated method show more reliable and reasonable values than those measured by thermal uncompensated system. This study suggests that the temperature-compensated method of the mini-cone may be a useful technique to obtain the more reliable resistances with minimizing the temperature effect.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11A
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• pp.902-911
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• 2003

Using InGaP/GaAs HBT power cells with a 2.0${\times}$20$\mu\textrm{m}$$^2$ emitter area of a unit HBT, a two stage MMIC power amplifier has been developed for IMT-2000 handsets. An active-bias circuit has been used for temperature compensation and reduction in the idling current. Fitting on measured S-parameters of the HBT cells, circuit elements of HBT's nonlinear equivalent model have been extracted. The matching circuits have been designed basically with the extracted model. A two stage HBT MMIC power amplifier fabricated using ETRI's HBT process. The power amplifier produces an 1-㏈ compressed output power(P$\_$l-㏈/) of 28.4 ㏈m with 31% power added efficiency(PAE) and 23-㏈ power gain at 1.95 GHz in on-wafer measurement. Also, the power amplifier produces a 26 ㏈m output power, 28% PAE and a 22.3-㏈ power gain with a -40 ㏈c ACPR at a 3.84 ㎒ off-center frequency in COB measurement.quency in COB measurement.

• Journal of the Korean Solar Energy Society
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• v.32 no.spc3
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• pp.245-254
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• 2012

In photovoltaic system, the characteristics of photovoltaic module such as open circuit voltage and short circuit current will be changed because of cell temperature and solar radiation. Therefore, the boost converter of a PV system connects between the output of photovoltaic system and DC link capacitor of grid connected inverter as controlling duty ratio for maximum power point tracking(MPPT). This paper shows the dynamic characteristics of the boost converter by comparing single-loop and two-loop control algorithm using both analog and digital control. Both proposed compensation methods have been verified with computer simulation to demonstrate the validity of the proposed control schemes.