• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.501-512
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• 2018

Radio frequency identification (RFID) sensor tag provides several advantages including battery-less operation and low cost, which are suitable for long-term monitoring. This paper presents a self-powered RFID temperature sensor tag for online temperature monitoring in substation. The proposed sensor tag is used to measure and process the temperature of high voltage equipments in substation, and then wireless deliver the data. The proposed temperature sensor employs a novel phased-locked loop (PLL)-based architecture and can convert the temperature sensor in frequency domain without a reference clock, which can significantly improve the temperature accuracy. A two-stage rectifier adopts a series of auxiliary floating rectifier to boost its gate voltage for higher power conversion efficiency. The sensor tag chip was fabricated in TSMC $0.18{\mu}m$ 1P6M CMOS process. The measurement results show that the proposed temperature sensor tag achieve a resolution of $0.15^{\circ}C$/LSB and a temperature error of $-0.6/0.7^{\circ}C$ within the range from $-30^{\circ}C$ to $70^{\circ}C$. The proposed sensor tag achieves maximum communication distance of 11.8 m.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1741-1748
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• 2005

In this paper, we describe VLSI design and performance evaluation of OCB-AES crytographic algorithm that simulataneously provides privacy and authenticity. The OCB-AES crytographic algorithm sovles the problems such as long operation time and large hardware of conventional crytographic system, because the conventional system must implement the privancy and authenticity sequentially with seqarated algorithms and hardware. The OCB-AES processor with area-efficient modular offset generator and tag generator is designed using IDEC Samsung 0.35um standard cell library and consists of about 55,700 gates. Its cipher rate is about 930Mbps and the number of clock cycles needed to generate the 128-bit tags for authenticity and integrity is (m+2)${\times}$(Nr+1), where m and Nr represent the number of block for message and number of rounds for AES encryption, respectively. The OCB-AES processor can be applicable to soft cryptographic IP of IEEE 802.11i wireless LAN and Mobile SoC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.826-832
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• 2004

A CMOS 8 bit folding and interpolating ADC for an embedded system inside VLSI is presented in this paper. This folding ADC uses the 2 stage architecture for improving of nonlinearity. repeating the folding and interpolating twice. At a proposed structure, a transistor differential pair operates on the second folder. A ADC with 2 stage architecture reduces the number of comparators and resisters. So it is possible to provide small chip size, low power consumption and high operating speed. The design technology is based on fully standard 0.25m double-Poly 2 metal n-well CMOS Process. The simulated Power consumption is 45mW with an applied voltage of 2.5V and sampling frequency of 250MHz. The INL and DNL are within <ㅆㄸㅌ>$\pm$0.2LSB, respectively. The SNDR is approximately 45dB for input frequency of 10MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1103-1108
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• 2010

In this paper, Frequency Synthesizer which is widely used for FH-SS system is proposed and the experimental results are analyzed. The performance of the DPLL(Digital Phase-Locked-Loop), which is the main part of the Synthesizer is analyzed by the computer program. Using Maxplus-II tool provided by altera. co., ltd, each part of the DPLL is designed and all of them is integrated into EPM7064SLC44-10 chip. And the simulation results are compared with the characteristics of the implemented circuits for analysis. And the experiential results show that the N value of the loop filter is toggled to adjacent N value, which result in phase jitter of the output. It can be resolved by increasing DCO(Digital Controlled oscillator) clock rate.

• Journal of Sensor Science and Technology
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• v.20 no.2
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• pp.131-136
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• 2011

In this study, a compact wireless vibration measurement system was developed using a 3-axial accelerometer in order to evaluate the vibration stimulation system. A low power microprocessor chip integrated with 2.4 GHz RF transceiver was used for the wireless data communication. To evaluate the system, the frequencies and accelerations from the vibration stimulation system were measured using an LVDT sensor and a vibration measurement system. The average frequency difference by the measurement system was less than 0.1 Hz, and the standard deviation of frequencies estimated by the LVDT sensor and the accelerometer was below 0.08 Hz. The developed system was applied to access a vibration stimulation system for the future study. The average acceleration difference of the central and peripheral point of the stimulation system was less than 0.0005 g(1 g=9.8 $m/s^2$), and the standard deviation of the acceleration was below 0.004 g, which shows the usefulness of the wireless vibration measurement system.

• Journal of Sensor Science and Technology
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• v.2 no.1
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• pp.19-27
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• 1993

Capacitive pressure sensor for low pressure measurements has been fabricated by using $n^{+}$ epitaxial layer electrochemical etching stop and glass-to-silicon electrostatic bonding technique. The sensor had hybrid configuration of a sensor chip, which consists of sensor capacitor and reference capacitor, and two output signal detection IC chips. A fabricated sensor, with a $1.0{\times}1.0 mm^{2}$ square size and a $10{\mu}m$ thick flat diaphragm, showed a 7.1 pF zero pressure capacitance, and 5.2 % F.S, sensitivity in 10 KPa pressure range. By using a capacitance to voltage converter, the thermal zero shift of 0.051 %F.S./$^{\circ}C$ and the thermal sensitivity shift of 0.12 %F.S./$^{\circ}C$ for temperature range of $5{\sim}45^{\circ}C$ were obtained.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.14-24
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• 2002

In this paper, a design of the pulsewidth-modulation(PWM) neural network with both retrieving and learning function is proposed. In the designed PWM neural system, the input and output signals of the neural network are represented by PWM signals. In neural network, the multiplication is one of the most commonly used operations. The multiplication and summation functions are realized by using the PWM technique and simple mixed-mode circuits. Thus, the designed neural network only occupies the small chip area. By applying some circuit design techniques to reduce the nonideal effects, the designed circuits have good linearity and large dynamic range. Moreover, the delta learning rule can easily be realized. To demonstrate the learning capability of the realized PWM neural network, the delta learning nile is realized. The circuit with one neuron, three synapses, and the associated learning circuits has been designed. The HSPICE simulation results on the two learning examples on AND function and OR function have successfully verified the function correctness and performance of the designed neural network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.12
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• pp.2865-2874
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• 2013

Recently, most of movies top-ranked in the box office are screening in Stereoscopic 3D, and the world's leading electronics companies such as Samsung and LG are getting the hots for 3DTV sales. However, each person has different binocular disparity and different viewing distance, and thus he or she feels the severe visual fatigue and headaches if he or she is watching 3D content with the same binocular disparity, which is very different from things he or she feels in the real world. To solve this problem, this paper proposes and implement a 3D rendering system that correct the disparity of 3D content by reflecting binocular distance and viewing distance. Then, the computational complexity is analyzed. Optical-flow and Warping algorithms turn out to consume 732 seconds and 5.7 seconds per frame, respectively. Therefore, a dedicated chip-set for both blocks is strongly required for real-time HD 3D display.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.1
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• pp.130-136
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• 2008

This paper describes a low-power high-performance analog front-end block for $UHF(860{\sim}960MHz)$ band RFID tag chips. It satisfies ISO/IEC 18000-6 type C(EPCgolbal class1. generation2.) and includes a memory block for test. For reducing power consumption, it operates with a internally generated power supply of 1V. An ASK demodulator using a current-mode schmitt trigger is proposed and designed. The proposed demodulator has an error rate as low as 0.014%. It is designed using a 0.18um CMOS technology. The simulation results show that the designed circuit can operate properly with an input as low as $0.2V_{peak}$ and consumes $2.63{\mu}A$. The chip size is $0.12mm^2$