• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.263-264
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of 0.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation or in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA implementation results for the proposed structure show 39% and 32% gate count reduction comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• Journal of the Optical Society of Korea
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• v.16 no.3
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• pp.203-209
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• 2012

Visible light communications (VLC) use modern solid-state light-emitting diodes (LEDs) to broadcast information. Emerging white-light LEDs allow the combination of lighting and optical wireless communication in one optical source. In this paper, a new LED lighting design using one-chip-type white LEDs is proposed for efficient illumination and optical wireless communications under the existence of several obstacles. Lighting and communication performance are analyzed to show the effectiveness of the proposed LED lighting. Specifically, the signal-to-noise ratio considering intersymbol interference and the bit-error rate of variable pulse position modulation (VPPM) with dimming control are considered.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.9
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• pp.546-553
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• 2000

W e have developed a power line simulator which is one of the basic tools for the research of the power line communication and its control system. In the developed simulators, we have considered the transfer function of the power line, noises and signal attenuation characteristics. Simulator was made using the matlab tool program. We made the power line modem using the FSK chip(ST7537) and experimentalized to show the efficiency grade of simulator. We have expected that the developed simulators are very useful in the area for the power line communication research and the control system design.

• Current Optics and Photonics
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• v.6 no.1
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• pp.15-22
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• 2022

This paper describes the construction of a phase shifter with low loss and small volume. To construct it, we use the two graphene layers that are separated by a hexagonal boron nitride (hBN) and embedded in a silicon waveguide. The refractive index of the waveguide is adjusted by applying a bias voltage to the graphene sheet to create an optical phase shift. This waveguide is a compact device that only has a radius of 5 ㎛. It has a phase shift of 6π. In addition, the extinction ratio (ER) is 11.6 dB and the insertion loss (IL) is 0.031 dB. Due to its unique characteristics, this device has great potential in silicon on-chip optical interconnection and all-optical multiple-input multiple-output processing.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8B
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• pp.668-676
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• 2012

In this paper, on the assumption that MPI collective communication function is converted into a group of point-to-point communication functions in the transaction level, an algorithm that optimizes broadcast, scatter and gather function among MPI collective communication is proposed. The MPI hardware engine that operates the proposed algorithm was designed, and it was named the OCC-MPE (Optimized Collective Communication Message Passing Engine). The OCC-MPE operates point-to-point communication by using the standard send mode. The transmission order is arranged according to the algorithm that proposes the most frequently used broadcast, scatter and gather functions among the collective communications, so the whole communication time is reduced. To measure the performance of the proposed algorithm, the OCC-MPE with the Bus Functional Model (BFM) based on SystemC was designed. After evaluating the performance through the BFM based on SystemC, the proposed OCC-MPE is designed by using VerilogHDL. As a result of synthesizing with the TSMC $0.18{\mu}m$, the gate count of each OCC-MPE is approximately 1978.95 with four processing nodes. That occupies approximately 4.15% in the whole system, which means it takes up a relatively small amount. Improved performance is expected with relatively small amounts of area increase if the OCC-MPE operated by the proposed algorithm is added to the MPSoC (Multi-Processor System on a Chip).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.778-784
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• 2008

In this paper, a chip antenna using multi-layer configuration for multi-band operation, such as GSM, DCS, pcs, WCDMA, and Mobile WiMAX for 2.3 GHz is proposed. This proposed antenna is a PIFA structure with multi-layer configuration fabricated on R04003 substrate(${\varepsilon}_r=3.4$) and its size is $22{\times}5.5{\times}4.0\;mm^3$. Multi-layer structure can effectively reduce the size of an antenna from a reuse of air-space and can achieve broad bandwidth due to decrement of parallel capacitances from the insertion air-gap to the middle layer. The proposed antenna has a broadband operation by the high order resonance modes and the resonance at the top layer. The measured bandwidths with over 45 % radiation efficiency are 80 MHz($880{\sim}960\;MHz$) at the lower band and 690 MHz($1,710{\sim}2,400\;MHz$) at the higher band.

• Journal of information and communication convergence engineering
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• v.9 no.6
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• pp.729-732
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• 2011

Power consumption during testing System-On-Chip (SOC) is becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1757-1762
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• 2003

With distribution industrial control system, the use of low cost to achieve a highly reliable and safe system in real time distributed embedded application is proposed. This developed intelligent node is based on two microcontrollers, one for the execution of the application code, also as master controller for ensuring the real time control & the logic operation with PLD and other for communication task and the easy control execution, i.e., I/O digital input, digital output and interrupting. This paper also presents where the case NCS (Networked control system) with LonTalk protocol is applied for the filtration process control system of a small water treatment plant.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.411-414
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• 2004

This paper introduces a modulation method for digital wireless communication based on general DS-QPSK. The design and fabrication is for home networking application to a typical RF transmitter with DS-QPSK modulator. This modulator implemented using VHDL hardware programming language, the fabrication of IC chip $5{\times}5 mm^2$ was carried by 27th IDEC MPW(Multi Project Wafer) process in 0.35${\mu}m$ rule at Samsung Inc. This paper presented the important of this technology for the future application in wireless sensor. This module can be efficient usage for home network to transmit the RF wireless sensor system.

• ETRI Journal
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• v.37 no.1
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• pp.118-127
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• 2015

The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.