• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.49-55
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• 2015

This paper proposes a 2.4 GHz RF oscillator with a very low close-in phase noise performance. This is composed of a low frequency crystal oscillator and three frequency multipliers such as two doubler (X2) and one tripler (X3). The proposed oscillator is implemented as a hybrid type circuit design using a discrete silicon bipolar transistor. The measurement results of the proposed oscillator structure show -115 dBc/Hz close-in phase noise at 10 kHz offset frequency, while only dissipating 5 mW from a 1-V supply. Its close-in phase noise level is very close to that of a low frequency crystal oscillator with little degradation of noise performance. The proposed structure which is consisted of a low frequency crystal oscillator and a frequency multiplier provides new method to implement a low power low close-in phase noise RF local oscillator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.146-153
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• 2008

In this paper, a integrated phase-locked loop(PLL) as a clock multiphase generator for a high speed serial link is designed. The designed PLL keeps the same bandwidth and damping factor by using programmable current mirror in the whole operation frequency range. Also, the close-loop transfer function and VCO's phase-noise transfer function of the designed PLL are obtained with circuit netlists. The self impedance on board-mounted chip is calculated according to sizes and positions of decoupling capacitors. Especially, the detailed self-impedance analysis is carried out between frequency ranges represented the maximum gain in the close-loop transfer function and the maximum gain in the VCO's phase noise transfer function. We shows PLL's jitter characteristics by decoupling capacitor's sizes and positions from this result. The designed PLL has the wide operating range of 0.4GHz to 2GHz in operating voltage of 1.8V and it is designed 0.18-um CMOS process. The reference clock is 100MHz and PLL power consumption is 17.28mW in 1.2GHz.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.26 no.12
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• pp.2535-2540
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• 2002

ESPI is a noncontact, nondestructive and relatively fast inspection method. For these reasons ESPI is being applied as a valuable tool in the nondestructive evaluation of structural components. Phase shifting ESPI is used more effectively than the traditional ESPI because spatial resolution of small object displacements are improved and numerical phase values are obtained for all pixels in the image. Consequently the quantitative measurement of deformation is possible. ESPI fringe patterns are contaminated with high levels of speckle noise. Therefore the phase image is to be smoothed to remove the noise and obtain a better signal-to-noise ratio. In this study, smoothing is done by phase shifting convolution to avoid smoothing errors close to the 2$\pi$ phase ambiguities in the deformation phase image, and median filter is used as a smoothing filter.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.605-615
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• 1986

The phase-locked loop(PLL) is a communication receiver which operates as a coherent detector by continuously correcting the phase error. In this paper analysis for the Phase-error behavior of analog phase-locked loop (APLL) in the presence of additive white gaussian noise has been done theoretically and experimentally. A close form solution of the first-order loop is obtained and approximate solutions are derived for the second-order loops with RC, leadlag and perfect integrator filters. The perdormance of APLL's and their characteristics are also thoroughly investigated through experiments. In order to analyze the effect of the stochastic nature on nonlinear dynamics characteristics of the second order APLL, the phase error distribution and its variance have been obtained by using the Fokker-Planck equation. Theoretical results agree closely with those of experiment.

• Journal of radiological science and technology
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• v.40 no.2
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• pp.245-251
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• 2017

This study measured the exposure dose during abdominal-pelvic CT exam which occupies 70% of CT exam and tried to propose a protocol for optimized exposure dose in abdomen and pelvis without affecting the imagery interpretation. The study scanned abdomen-pelvis using the current clinical scan method, the 120 kVp, auto exposure control(AEC), as 1 phase. As for the newly proposed 2 phase scan method, the study divided into 1 phase abdomen exam and 2 phase pelvis exam and each conducted tube voltage 120 kVp, AEC for abdomen exam, and fixed tube current method in 120 kVp, 100, 150, 200, 250, 300, 350, 400 mA for pelvis exam. The exposure dose value was compared using $CTDI_{VOL}$, DLP value measured during scan, and average value of CT attenuation coefficient, noise, SNR from each scan image were obtained to evaluate the image. As for the result, scanning of 2 phase showed significant difference compared to 1 phase. In $CTDI_{VOL}$ value, the 2 phase showed 26% decrease in abdomen, 1.8~59.5% decrease in pelvis for 100~250 mA, 12.7%~30% increase in pelvis for 300~400 mA. Also, DLP value showed 53% decrease in abdomen and 41~81% decrease in pelvis when scanned by 2 phase compared to 1 phase, but it was not statistically significant. As for the SNR, when scanning 2 phase close to heart, scanning 1 phase close to pelvis, scanning and scanning 1 phase at upper and lower abdomen, it was higher when scanning 2 phase for 200~250 mA. Also, the CT number and noise was overall similar, but the noise was high close to pelvis. However, when scanning 2 phase for 250 mA close to pelvis, the noise value came out similar to 1 phase, and did not show statistically significant difference. It seems when separating pelvis to scan in 250 mA rather than 400 mA in 1 phase as before, it is expected to have reduced effect of exposure dose without difference in the quality of image. Thus, for patients who often get abdominal-pelvic CT exam, fertile women or children, this study proposes 2 phase exam for smaller exposure dose with same image quality.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.7
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• pp.635-645
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• 2016

In this paper, we showed the phase noise of voltage controlled oscillator(VCO) can be radically improved using FLL(Frequency Locked Loop). At first, a 5 GHz VCO is fabricated using a hair-pin resonator. The fabricated VCO shows a phase noise of -53.1 dBc/Hz at 1 kHz frequency offset. In order to improve the phase noise of the fabricated VCO, a FLL is constructed using the feedback loop that consists of the VCO, a frequency detector composed of 5 GHz resonator, loop-filter, and level shifter. The fabricated FLL is designed to oscillate at a frequency of 5 GHz, and its measured phase noise is about -120.6 dBc/Hz at 1 kHz offset frequency. As a result, the phase noise of VCO can be radically improved by about 67.5 dB applying FLL. In addition, the measured phase noise performance is close to that of crystal oscillator.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2002.05a
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• pp.633-638
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• 2002

The vacuum cleaner that has no dust bag generates very high level annoying noise. The dominant noise source is the 2$\^$nd/ BPF tone of the rotating impeller. In order to reduce the noise, we identify the acoustic characteristics and reduce the noise of the vacuum cleaner and centrifugal fan. The resonance phenomenon is observed in blade passages and we found out that the resonance frequency is very close to the 2$\^$nd/ BPF. In order to reduce this high-level peak noise, new impeller is designed in this paper. The trailing edge of new impeller is inclined and this makes the flow interactions between the rotating impeller and the stationary diffuser vane occurs with some phase shift. The performance of new impeller is similar to the old one but the overall SPL is reduced about 3.6dBA. The SPL of BPF is reduced about 6dBA and 2$\^$nd/ BPF is reduced about 20dBA. The vacuum cleaner, which uses newly developed centrifugal fan, generate more comfortable noise than the old model and the strong tonal sound was dramatically reduced.

• The Journal of the Acoustical Society of Korea
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• v.30 no.1
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• pp.42-48
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• 2011

This preliminary study is about the application of the compound source to the active noise barrier system as control sources. A compound source is composed of two monopole sources but having opposite phase. However, both monopole sources in one compound source are not independently controlled. The source strength of monopole source close to the noise source is proportional to the other one. Therefore, the cost for the hardware system is cheaper than usual system but known to possibly having a similar performance in generating anti-noise acoustic field. In this study, using a simple active noise barrier system model having a non-reflective floor, the effectiveness of the system with compound sources is investigated through computer simulations and shows 30~40 % performance improvement of noise reduction.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• Journal of the Korea Safety Management & Science
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• v.17 no.4
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• pp.403-410
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• 2015

This study documents the 3-phase BLDC(Brushless DC) motor to improve conventional exhaust fan motor. Energy efficiency, noise, and air pollution reduction for the high-performance vibration of the BLDC motor has been used in many fields. It is necessary to achieve the information of rotor position for driving 3-phase type brushless DC motor. It is also necessary that the PWM control algorithm design for a MOSFET driver to control the motor speed control for each of three phases. BLDC motors for exhaust fan, we studied the controller and software. The control circuit and motor control program through which Exhaust fan up close and person can be used safely and protect the environment.